Farid Lahrach

According to our database, Farid Lahrach authored at least 5 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Tolérance aux pannes des circuits FPGAs à base de mémoire SRAM. (Fault tolerance of SRAM-based FPGAs circuits).

Farid Lahrach

PhD thesis, 2016

2011

Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems.

Farid Lahrach, Abderrahim Doumar, Eric Châtelet

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Fault tolerance of SRAM-based FPGA via configuration frames.

Farid Lahrach, Abderrahim Doumar, Eric Châtelet

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA.

Farid Lahrach, Abderrahim Doumar, Eric Châtelet, Abderrazek Abdaoui

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks.

Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010