Farhad Merchant
Orcid: 0000-0002-3708-5621
According to our database1,
Farhad Merchant
authored at least 66 papers
between 2011 and 2024.
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Bibliography
2024
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms.
CoRR, 2024
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL.
CoRR, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the IEEE European Test Symposium, 2024
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., December, 2023
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.
IEEE Embed. Syst. Lett., December, 2023
J. Syst. Archit., February, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security.
IEEE Des. Test, 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach.
ACM J. Emerg. Technol. Comput. Syst., 2021
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems.
IEEE Access, 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit.
IEEE Access, 2020
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020
2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
2018
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.
IEEE Trans. Parallel Distributed Syst., 2018
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.
CoRR, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Parallel Process. Lett., 2017
2016
CoRR, 2016
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
2015
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.
Proceedings of the 28th International Conference on VLSI Design, 2015
2014
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.
J. Syst. Archit., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2011
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support.
Proceedings of the International Symposium on Electronic System Design, 2011