Faquir C. Jain

Orcid: 0000-0003-3961-6665

Affiliations:
  • University of Connecticut, Storrs, USA


According to our database1, Faquir C. Jain authored at least 18 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Eight-bit ADC using non-volatile flash memory.
IET Circuits Devices Syst., 2019

Highly Linear Amperometric Glucose Detection System Realized in Deep Submicron CMOS Technology.
Proceedings of the IEEE International Symposium on Medical Measurements and Applications, 2019

2017
Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Application of quantum dot gate nonvolatile memory (QDNVM) in image segmentation.
Signal Image Video Process., 2016

2015
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Three-state quantum dot gate field-effect transistor in silicon-on-insulator.
IET Circuits Devices Syst., 2015

Needle-implantable, wireless biosensor for continuous glucose monitoring.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

2014
Implementation of Six Bit ADC and DAC Using Quantum Dot Gate Non-Volatile Memory.
J. Signal Process. Syst., 2014

2013
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A low power miniaturized CMOS-based continuous glucose monitoring system.
Proceedings of the 2013 IEEE International Conference on Body Sensor Networks, 2013

2012
Theoretical Analysis of the Performance of Glucose Sensors with Layer-by-Layer Assembled Outer Membranes.
Sensors, 2012

2009
Analysis of Defect Tolerance in Molecular Crossbar Electronics.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation.
ACM J. Emerg. Technol. Comput. Syst., 2009

Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing.
ACM J. Emerg. Technol. Comput. Syst., 2009

2008
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Programmable threshold voltage using quantum dot transistors for low-power mobile computing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Dynamic redundancy allocation for reliable and high-performance nanocomputing.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Analysis of defect tolerance in molecular electronics using information-theoretic measures.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007


  Loading...