Fangyuan Dong
Orcid: 0009-0004-8025-7849
According to our database1,
Fangyuan Dong
authored at least 6 papers
between 2017 and 2024.
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Bibliography
2024
A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
IEEE J. Solid State Circuits, September, 2024
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2017
Proceedings of the 2017 IEEE International Conference on Signal Processing, 2017