Fangxu Lv
Orcid: 0000-0001-8301-0359
According to our database1,
Fangxu Lv
authored at least 26 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
Microelectron. J., October, 2023
Proceedings of the 4th International Conference on Computer Engineering and Intelligent Control, 2023
Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023
2022
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J., 2022
2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Microelectron. J., 2018
2017
IEEE J. Solid State Circuits, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network.
Proceedings of the Advances in Wireless Sensor Networks - The 8th China Conference, 2014