Fangxu Lv

According to our database, Fangxu Lv authored at least 30 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization.

Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.

Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface.

Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu

Microelectron. J., 2024

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.

Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang

Microelectron. J., 2024

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process.

Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao

IEICE Electron. Express, 2024

A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE.

Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu

IEICE Electron. Express, 2024

FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver.

Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM.

Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology.

Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu

Microelectron. J., October, 2023

Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.

Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv

Proceedings of the 4th International Conference on Computer Engineering and Intelligent Control, 2023

A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.

Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu

Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023

2022

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.

Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi

Microelectron. J., 2022

2021

An Adaptive Equalization Algorithm for High Speed SerDes.

Miaomiao Wu, Zhengbin Pang, Fangxu Lv, Jianjun Shi, Heming Wang, Tao Liu, Dechao Lu, Zheng Wang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.

Tao Liu, Fangxu Lv, Bin Liang, Heming Wang, Jianye Wang, Miaomiao Wu

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.

Geng Zhang, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators.

Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu

IEEE J. Solid State Circuits, 2020

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.

Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu

IEEE J. Solid State Circuits, 2020

A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology.

Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu

Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2019

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology.

Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.

Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang

Microelectron. J., 2018

2017

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.

Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang

IEEE J. Solid State Circuits, 2017

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.

Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.

Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan, Chun Zhang, Zhihua Wang, Hanjun Jiang

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS.

Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.

Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.

Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.

Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.

Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network.

Yu Wang, Jincheng Zhang, Quan Wang, Fangxu Lv, Kewei Chen

Proceedings of the Advances in Wireless Sensor Networks - The 8th China Conference, 2014