Fangfei Liu

Orcid: 0009-0001-8355-7028

According to our database1, Fangfei Liu authored at least 18 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Wryneck Tree: Designing a Multimodal Interactive System for Sedentary Office Forward Head Postures Correction.
Proceedings of the Entertainment Computing - ICEC 2023, 2023

The Strength Assistant Gloves Interaction Development for Female Employment by EMG Signal Visualization Image Analysis.
Proceedings of the HCI International 2023 Posters, 2023

CacheFX: A Framework for Evaluating Cache Security.
Proceedings of the 2023 ACM Asia Conference on Computer and Communications Security, 2023

2022
Chameleon Cache: Approximating Fully Associative Caches with Random Replacement to Prevent Contention-Based Cache Attacks.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

2021
Underwater Image Restoration and Enhancement via Residual Two-Fold Attention Networks.
Int. J. Comput. Intell. Syst., 2021

Speculative interference attacks: breaking invisible speculation schemes.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2018
Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses.
Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018

2017
Cloud Server Benchmark Suite for Evaluating New Hardware Architectures.
IEEE Comput. Archit. Lett., 2017

2016
Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks.
IEEE Micro, 2016

Cloud Server Benchmarks for Performance Evaluation of New Hardware Architecture.
CoRR, 2016

CATalyst: Defeating last-level cache side channel attacks in cloud computing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Mapping the Intel Last-Level Cache.
IACR Cryptol. ePrint Arch., 2015

Last-Level Cache Side-Channel Attacks are Practical.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

Can randomized mapping secure instruction caches from side-channel attacks?
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Random Fill Cache Architecture.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Side channel vulnerability metrics: the promise and the pitfalls.
Proceedings of the HASP 2013, 2013

Security testing of a secure cache design.
Proceedings of the HASP 2013, 2013


  Loading...