Fakhreddine Ghaffari

IEEE Commun. Lett., July, 2023

Optimal Sensor Set for Decoding Motor Imagery from EEG.

[BibT_eX]

[DOI]

Proceedings of the 11th International IEEE/EMBS Conference on Neural Engineering, 2023

Layout-based reliability analysis of openMSP430 register file under external radiations.

[BibT_eX]

[DOI]

Vivek Bansal

Otmane Aït Mohamed

Proceedings of the International Conference on Microelectronics, 2023

2021

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Reduced Complexity of a Successive Cancellation Based Decoder for NB-Polar Codes.

[BibT_eX]

[DOI]

F. Cochachin

Laura Luzzi

Proceedings of the 11th International Symposium on Topics in Coding, 2021

An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2019

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

David Declercq

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

An Adaptation of Min-Sum Decoder for 5G Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

Khoa LeTrung

David Declercq

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia-Pacific Conference on Communications, 2019

An Enhanced Offset Min-Sum decoder for 5G LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia-Pacific Conference on Communications, 2019

2018

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders.

[BibT_eX]

[DOI]

Thien Truong Nguyen-Ly

IEEE Trans. Very Large Scale Integr. Syst., 2018

Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2018

On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems.

[BibT_eX]

[DOI]

David Declercq

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels.

[BibT_eX]

[DOI]

Bane Vasic

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory.

[BibT_eX]

[DOI]

Constantina-Elena Gavriliu

Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

2017

A Hardware/Software Prototype of EEG-based BCI System for Home Device Control.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Probabilistic model of AFDX frames reception for end system backlog assessment.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA static timing analysis enhancement based on real operating conditions.

[BibT_eX]

[DOI]

Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Efficient FPGA implementation of probabilistic gallager B LDPC decoder.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Multi-Mode Low-Latency Software-Defined Error Correction for Data Centers.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Communication and Networks, 2017

Error rate estimation of a design implemented in an FPGA based on the operating conditions.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016

Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Influence of high-power electric motor on an FPGA used in the drive system of electric car.

[BibT_eX]

[DOI]

Proceedings of the IECON 2016, 2016

Non-surjective finite alphabet iterative decoders.

[BibT_eX]

[DOI]

Thien Truong Nguyen-Ly

Proceedings of the 2016 IEEE International Conference on Communications, 2016

Online Adaptive Filters to Classify Left and Right Hand Motor Imagery.

[BibT_eX]

[DOI]

Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

2015

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders.

[BibT_eX]

[DOI]

Andrei Hera

Oana Boncalo

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Efficient realization of probabilistic gradient descent bit flipping decoders.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Reliability assessment of backward error recovery for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Design and Test Symposium, 2014

Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Marc Alexandre Kacou

Olivier Romain

Proceedings of the 26th International Conference on Microelectronics, 2014

An embedded implementation of home devices control system based on brain computer interface.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Microelectronics, 2014

2013

An efficient BER-based reliability method for SRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

2011

Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2011

2010

Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications.

[BibT_eX]

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture.

[BibT_eX]

[DOI]

Proceedings of the 5th International Design and Test Workshop, 2010

2009

Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures.

[BibT_eX]

[DOI]

Benoît Miramond

François Verdier

EURASIP J. Embed. Syst., 2009

2008

Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip.

[BibT_eX]

[DOI]

Benoît Miramond

François Verdier

Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

2007

Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2007

2006

An efficient on-line Approach for on-chip HW/SW partitioner and scheduler.

[BibT_eX]

[DOI]