Faiq Khalid
Orcid: 0000-0001-6263-674XAffiliations:
- TU Wien, Vienna, Austria
According to our database1,
Faiq Khalid
authored at least 67 papers
between 2012 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
FM-ModComp: Feature Map Modification and Hardware-Software Co-Comparison for secure hardware accelerator-based CNN inference.
Microprocess. Microsystems, July, 2023
SeVuc: A study on the Security Vulnerabilities of Capsule Networks against adversarial attacks.
Microprocess. Microsystems, February, 2023
SHIELD: An Adaptive and Lightweight Defense against the Remote Power Side-Channel Attacks on Multi-tenant FPGAs.
CoRR, 2023
StAIn: Stealthy Avenues of Attacks on Horizontally Collaborated Convolutional Neural Network Inference and Their Mitigation.
IEEE Access, 2023
Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023
2022
ForASec: Formal Analysis of Hardware Trojan-Based Security Vulnerabilities in Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2L-3W: 2-Level 3-Way Hardware-Software Co-verification for the Mapping of Convolutional Neural Network (CNN) onto FPGA Boards.
SN Comput. Sci., 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities.
CoRR, 2021
Exploiting Vulnerabilities in Deep Neural Networks: Adversarial and Fault-Injection Attacks.
CoRR, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
InTrust-IoT: Intelligent Ecosystem based on Power Profiling of Trusted device(s) in IoT for Hardware Trojan Detection.
Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021
GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Toward Model Checking-Driven Fair Comparison of Dynamic Thermal Management Techniques Under Multithreaded Workloads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
SIMCom: Statistical sniffing of inter-module communications for runtime hardware trojan detection.
Microprocess. Microsystems, 2020
IEEE Des. Test, 2020
MacLeR: Machine Learning-based Run-Time Hardware Trojan Detection in Resource-Constrained IoT Edge Devices.
CoRR, 2020
Is Spiking Secure? A Comparative Study on the Security Vulnerabilities of Spiking and Deep Neural Networks.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Using gate-level side channel parameters for formally analyzing vulnerabilities in integrated circuits.
Sci. Comput. Program., 2019
SNN under Attack: are Spiking Deep Belief Networks vulnerable to Adversarial Examples?
CoRR, 2019
CoRR, 2019
CoRR, 2019
SIMCom: Statistical Sniffing of Inter-Module Communications for Run-time Hardware Trojan Detection.
CoRR, 2019
IEEE Access, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
TrISec: Training Data-Unaware Imperceptible Security Attacks on Deep Neural Networks.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Building Robust Machine Learning Systems: Current Progress, Research Challenges, and Opportunities.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Runtime hardware Trojan monitors through modeling burst mode communication using formal verification.
Integr., 2018
CoRR, 2018
SSCNets: A Selective Sobel Convolution-based Technique to Enhance the Robustness of Deep Neural Networks against Security Attacks.
CoRR, 2018
ISA4ML: Training Data-Unaware Imperceptible Security Attacks on Machine Learning Modules of Autonomous Vehicles.
CoRR, 2018
CoRR, 2018
McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits.
IEEE Access, 2018
Proceedings of the 2018 Annual IEEE International Systems Conference, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Security for Machine Learning-Based Systems: Attacks and Challenges During Training and Inference.
Proceedings of the 2018 International Conference on Frontiers of Information Technology, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
FAMe-TM: Formal analysis methodology for task migration algorithms in Many-Core systems.
Sci. Comput. Program., 2017
Behavior profiling of power distribution networks for runtime hardware trojan detection.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification.
J. Electron. Test., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Synchronously triggered GALS design templates leveraging QDI asynchronous interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Formal Verification of Gate-Level Multiple Side Channel Parameters to Detect Hardware Trojans.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2016
2015
Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection.
Proceedings of the Nordic Circuits and Systems Conference, 2015
2014
Timing variation aware dynamic digital phase detector for low-latency clock domain crossing.
IET Circuits Devices Syst., 2014
Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Formal Verification of Distributed Task Migration for Thermal Management in On-Chip Multi-core Systems Using nuXmv.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2014
2012
Modified null convention logic pipeline to detect soft errors in both null and data phases.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012