Fahim Rahman
Orcid: 0000-0001-9388-0112
According to our database1,
Fahim Rahman
authored at least 59 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
IEEE Des. Test, August, 2024
ACM Trans. Design Autom. Electr. Syst., January, 2024
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.
IEEE Access, 2024
SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations.
IEEE Des. Test, October, 2023
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology.
IEEE Des. Test, April, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the IEEE European Test Symposium, 2023
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification.
IEEE Trans. Consumer Electron., 2022
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance.
IACR Cryptol. ePrint Arch., 2022
Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications.
IACR Cryptol. ePrint Arch., 2022
PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch., 2022
Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions.
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.
ACM Trans. Design Autom. Electr. Syst., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the IEEE International Test Conference, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Prediction And Detection In Change Of Cognitive Load For VIP's By A Machine Learning Approach.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence in Engineering and Technology, 2021
AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification.
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
CoRR, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
IACR Cryptol. ePrint Arch., 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference, 2019
FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Multi Scale Comput. Syst., 2017
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017
2016
IEEE Trans. Emerg. Top. Comput., 2016
Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015
A pair selection algorithm for robust RO-PUF against environmental variations and aging.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015