Fahad Bin Muslim

According to our database, Fahad Bin Muslim authored at least 15 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Securing the IoT ecosystem: ASIC-based hardware realization of Ascon lightweight cipher.

Safiullah Khan, Kashif Inayat, Fahad Bin Muslim, Yasir Ali Shah, Muhammad Atif Ur Rehman, Ayesha Khalid, Malik Imran, Akmalbek Abdusalomov

Int. J. Inf. Sec., December, 2024

FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach.

Kashif Inayat, Fahad Bin Muslim, Tayyeb Mahmood, Jaeyong Chung

J. Syst. Archit., 2024

LPCHISEL: Automatic power intent generation for a chisel-based ASIC design.

Fahad Bin Muslim, Kashif Inayat, Safiullah Khan

Comput. Electr. Eng., 2024

2023

Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration.

Kashif Inayat, Fahad Bin Muslim, Javed Iqbal, Syed Agha Hassnain Mohsan, Hend Khalid Alkahtani, Samih Mohemmed Mostafa

Sensors, 2023

2020

FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs.

Ali Zahir, Shadan Khan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad

IEEE Trans. Very Large Scale Integr. Syst., 2020

Implementation of Symbol Timing Recovery for Estimation of Clock Skew.

S. M. Usman Hashmi, Muntazir Hussain, Fahad Bin Muslim, Kashif Inayat, Seong Oun Hwang

CoRR, 2020

Simulations and experimental validation of one cycle controlled nine-level inverter using FPGA.

Azhar Ul-Haq, Marium Jalal, Muhammad Aamir, Carlo Cecati, Fahad Bin Muslim, Arsalan Ahmad Raja, Javed Iqbal

Comput. Electr. Eng., 2020

2017

Energy-efficient hardware design based on high-level synthesis.

Fahad Bin Muslim

PhD thesis, 2017

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow.

Affaq Qamar, Fahad Bin Muslim, Javed Iqbal, Luciano Lavagno

Microprocess. Microsystems, 2017

High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?

Affaq Qamar, Fahad Bin Muslim, Francesco Gregoretti, Luciano Lavagno, Mihai Teodor Lazarescu

IEEE Access, 2017

Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis.

Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno

IEEE Access, 2017

2016

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL.

Fahad Bin Muslim, Alexandros Demian, Liang Ma, Luciano Lavagno, Affaq Qamar

Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis.

Liang Ma, Fahad Bin Muslim, Luciano Lavagno

Proceedings of the 2016 European Modelling Symposium, 2016

2015

Analysis and Implementation of the Semi-Global Matching 3D Vision Algorithm Using Code Transformations and High-Level Synthesis.

Affaq Qamar, Fahad Bin Muslim, Luciano Lavagno

Proceedings of the IEEE 81st Vehicular Technology Conference, 2015

Low power methodology for an ASIC design flow based on high-level synthesis.

Fahad Bin Muslim, Affaq Qamar, Luciano Lavagno

Proceedings of the 23rd International Conference on Software, 2015