Fady Abouzeid
Orcid: 0000-0001-8711-0664
According to our database1,
Fady Abouzeid
authored at least 25 papers
between 2009 and 2024.
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Online presence:
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Bibliography
2024
On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations.
IEEE Access, 2024
Proceedings of the IEEE European Test Symposium, 2024
2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2018
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2018
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 0.40pJ/cycle 981 μm<sup>2</sup> voltage scalable digital frequency generator for SoC clocking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
30% static power improvement on ARM Cortex<sup>®</sup>-A53 using static biasing-anticipation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
IEEE J. Solid State Circuits, 2015
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance.
Proceedings of the 38th European Solid-State Circuit conference, 2012
28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
ACM Trans. Design Autom. Electr. Syst., 2011
A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009