Fabrizio Lombardi
Orcid: 0000-0003-3152-3245Affiliations:
- Northeastern University, Boston, USA
According to our database1,
Fabrizio Lombardi
authored at least 551 papers
between 1984 and 2025.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2009, "For contributions to testing and fault tolerance of digital systems".
Timeline
1985
1990
1995
2000
2005
2010
2015
2020
2025
0
5
10
15
20
25
30
3
12
15
14
18
11
14
9
8
18
10
3
7
3
3
8
13
11
6
12
9
7
5
5
4
6
5
4
3
5
2
4
4
6
3
1
3
3
2
2
4
12
9
12
11
11
4
13
9
8
5
9
9
9
14
20
9
9
6
6
12
8
7
8
10
7
8
2
2
3
3
3
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on ece.neu.edu
On csauthors.net:
Bibliography
2025
IEEE Trans. Computers, January, 2025
2024
Concurrent Classifier Error Detection (CCED) in Large Scale Machine Learning Systems.
IEEE Trans. Reliab., December, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
IEEE Trans. Computers, September, 2024
Computer, August, 2024
Adaptive Resolution Inference (ARI): Energy-Efficient Machine Learning for Internet of Things.
IEEE Internet Things J., April, 2024
Learning the Error Features of Approximate Multipliers for Neural Network Applications.
IEEE Trans. Computers, March, 2024
Joint Learning and Channel Coding for Error-Tolerant IoT Systems Based on Machine Learning.
IEEE Trans. Artif. Intell., January, 2024
Understanding the Impact of Artificial Intelligence in Academic Writing: Metadata to the Rescue.
Computer, January, 2024
IEEE Trans. Inf. Forensics Secur., 2024
IEEE Trans. Emerg. Top. Comput., 2024
Guest Editorial: Special Section on "Approximate Data Processing: Computing, Storage and Applications".
IEEE Trans. Emerg. Top. Comput., 2024
Reducing the Energy Dissipation of Large Language Models (LLMs) with Approximate Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
IEEE Trans. Computers, July, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Attacking the Privacy of Approximate Membership Check Filters by Positive Concentration.
IEEE Trans. Computers, May, 2023
IEEE Trans. Computers, April, 2023
Delta Sigma Modulator-Based Dividers for Accurate and Low Latency Stochastic Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
The Byzantine Empire and Its Generals: An Ancient Empire Back to Life in Computer Security.
Computer, March, 2023
IEEE Trans. Very Large Scale Integr. Syst., 2023
IEEE Trans. Sustain. Comput., 2023
An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.
IEEE Trans. Emerg. Top. Comput., 2023
IEEE Trans. Emerg. Top. Comput., 2023
A Technique for Approximate Communication in Network-on-Chips for Image Classification.
IEEE Trans. Emerg. Top. Comput., 2023
IEEE Trans. Dependable Secur. Comput., 2023
IEEE Trans. Dependable Secur. Comput., 2023
Statistical modeling of adaptive neural networks explains co-existence of avalanches and oscillations in resting human brain.
Nat. Comput. Sci., 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Integrating Delta Modulation and Stochastic Computing for Real-time Machine Learning based Heartbeats Monitoring in Wearable Systems.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Netw. Serv. Manag., December, 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers.
IEEE Trans. Emerg. Top. Comput., 2022
Guest Editorial: Special Section on "To be Safe and Dependable in the Era of Artificial Intelligence: Emerging Techniques for Trusted and Reliable Machine Learning".
IEEE Trans. Emerg. Top. Comput., 2022
An Inexact Newton Method For Unconstrained Total Variation-Based Image Denoising by Approximate Addition.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Dependable Secur. Comput., 2022
Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog.
IEEE Trans. Dependable Secur. Comput., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Computers, 2022
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2022
HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the Approximate Computing, 2022
Proceedings of the Approximate Computing, 2022
Proceedings of the Approximate Computing, 2022
2021
AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication.
J. Signal Process. Syst., 2021
Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.
IEEE Trans. Sustain. Comput., 2021
IEEE Trans. Neural Networks Learn. Syst., 2021
IEEE Trans. Emerg. Top. Comput., 2021
Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP).
IEEE Trans. Emerg. Top. Comput., 2021
Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Emerg. Top. Comput., 2021
A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation.
IEEE Trans. Emerg. Top. Comput., 2021
AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets.
IEEE Trans. Aerosp. Electron. Syst., 2021
A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning.
IEEE Open J. Comput. Soc., 2021
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).
Integr., 2021
Long-range temporal correlations in the broadband resting state activity of the human brain revealed by neuronal avalanches.
Neurocomputing, 2021
Future Gener. Comput. Syst., 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Analyzing and Assessing Pollution Attacks on Bloom Filters: Some Filters are More Vulnerable than Others.
Proceedings of the 17th International Conference on Network and Service Management, 2021
2020
IEEE Trans. Veh. Technol., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
Result-Based Re-computation for Error-Tolerant Classification by a Support Vector Machine.
IEEE Trans. Artif. Intell., 2020
Proc. IEEE, 2020
Proc. IEEE, 2020
Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.
Proc. IEEE, 2020
IET Comput. Digit. Tech., 2020
IET Circuits Devices Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Embed. Comput. Syst., 2019
Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes.
IEEE Trans. Computers, 2019
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM).
IEEE Trans. Computers, 2019
IEEE Trans. Computers, 2019
Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation.
IEEE Trans. Computers, 2019
Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC).
IEEE Trans. Computers, 2019
Non-equilibrium critical dynamics of bursts in θ and δ rhythms as fundamental characteristic of sleep and wake micro-architecture.
PLoS Comput. Biol., 2019
Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications.
J. Signal Process. Syst., 2018
J. Signal Process. Syst., 2018
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Computers, 2018
IEEE Trans. Computers, 2018
IEEE Trans. Computers, 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2017
Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).
IEEE Trans. Multi Scale Comput. Syst., 2017
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017
IET Networks, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Reliab., 2016
IEEE Trans. Multi Scale Comput. Syst., 2016
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers, 2016
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems.
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
Reliability and Criticality Analysis of Communication Networks by Stochastic Computation.
IEEE Netw., 2016
Integr., 2016
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.
Integr., 2016
Integr., 2016
Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays.
IET Circuits Devices Syst., 2016
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT.
J. Electron. Test., 2016
IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures.
IEEE Trans. Reliab., 2015
IEEE Trans. Multi Scale Comput. Syst., 2015
IEEE Trans. Computers, 2015
IEEE Trans. Computers, 2015
IEEE Trans. Computers, 2015
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders.
IEEE Trans. Computers, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation.
IEEE Trans. Computers, 2014
IEEE Trans. Computers, 2014
Proceedings of the 9th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2014
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A system-level scheme for resistance drift tolerance of a multilevel phase change memory.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A low-power, high-performance approximate multiplier with configurable partial error recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
IEEE Trans. Computers, 2013
IEEE Trans. Computers, 2013
A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect.
IEEE Trans. Computers, 2013
Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects.
IET Comput. Digit. Tech., 2013
J. Electron. Test., 2013
Effects of Poisson noise in a IF model with STDP and spontaneous replay of periodic spatiotemporal patterns, in absence of cue stimulation.
Biosyst., 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
An information-theoretic analysis of quantum-dot cellular automata for defect tolerance.
ACM J. Emerg. Technol. Comput. Syst., 2010
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability.
Integr., 2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates.
IEEE Trans. Instrum. Meas., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
J. Electron. Test., 2009
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
J. Electron. Test., 2009
An Efficient Framework for Scalable Defect Isolation in Large Scale Networks of DNA Self-Assembly.
J. Electron. Test., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
Evaluation and Analysis of Heuristic Techniques for Vector Ordering of VLSI Test Sets.
IEEE Trans. Instrum. Meas., 2008
IEEE Trans. Ind. Informatics, 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
ACM J. Emerg. Technol. Comput. Syst., 2008
J. Electron. Test., 2008
J. Electron. Test., 2008
IEEE Des. Test Comput., 2008
A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
2007
Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing.
IEEE Trans. Instrum. Meas., 2007
IEEE Trans. Instrum. Meas., 2007
IEEE Trans. Computers, 2007
Microelectron. J., 2007
Analysis of missing and additional cell defects in sequential quantum-dot cellular automata.
Integr., 2007
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire.
J. Electron. Test., 2007
IEEE Des. Test Comput., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
IEEE Trans. Instrum. Meas., 2006
IEEE Trans. Instrum. Meas., 2006
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).
IEEE Trans. Computers, 2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Environmental-based characterization of SoC-based instrumentation systems for stratified testing.
IEEE Trans. Instrum. Meas., 2005
Evaluation, analysis, and enhancement of error resilience for reliable compression of VLSI test data.
IEEE Trans. Instrum. Meas., 2005
IEEE Trans. Instrum. Meas., 2005
IEEE Trans. Instrum. Meas., 2005
Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Computers, 2005
ACM J. Emerg. Technol. Comput. Syst., 2005
Int. J. Embed. Syst., 2005
J. Electron. Test., 2005
IEEE Des. Test Comput., 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
2004
IEEE Trans. Instrum. Meas., 2004
IEEE Trans. Instrum. Meas., 2004
IEEE Trans. Instrum. Meas., 2004
IEEE J. Solid State Circuits, 2004
J. Syst. Archit., 2004
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electron. Test., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
2003
IEEE Trans. Reliab., 2003
Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment.
IEEE Trans. Instrum. Meas., 2003
IEEE Trans. Instrum. Meas., 2003
IEEE Trans. Computers, 2003
Microelectron. J., 2003
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
Proceedings of the 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 2003
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.
Proceedings of the International Conference on Embedded Systems and Applications, 2003
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
IEEE Trans. Reliab., 2002
Quality enhancement of reconfigurable multichip module systems by redundancy utilization.
IEEE Trans. Instrum. Meas., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Testing and evaluating the quality-level of stratified multichip module instrumentation.
IEEE Trans. Instrum. Meas., 2001
IEEE Trans. Computers, 2001
Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems.
IEEE Des. Test Comput., 2001
Modeling the Dependability of N-Modular Redundancy on Demand under Malicious Agreement.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001
Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA 2001), 2001
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Computers, 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping.
Proceedings of the Parallel and Distributed Processing, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Test generation and scheduling for layout-based detection of bridge faults in interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Consumer Electron., 1999
J. Electron. Test., 1999
Guest Editors' Introduction: DRAM Architecture and Testing.
IEEE Des. Test Comput., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999
Proceedings of the Digest of Papers: FTCS-29, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
ACM Trans. Design Autom. Electr. Syst., 1998
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.
IEEE Trans. Computers, 1998
Field-Programmable Gate Arrays.
IEEE Des. Test Comput., 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the Modelling and Motion Capture Techniques for Virtual Environments, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Using Virtual Links for Reliable Information Retrieval Across Point-to-Point Networks.
Proceedings of the Digest of Papers: FTCS-27, 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
IEEE Trans. Computers, 1996
SIAM J. Discret. Math., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '96), 1996
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996
Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995
Diagnosing Multiple Bridge Faults in Baseline Multistage Interconnection Networks.
Proceedings of the 1995 International Conference on Parallel Processing, 1995
A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems.
Proceedings of the 1995 International Conference on Parallel Processing, 1995
Proceedings of the Digest of Papers: FTCS-25, 1995
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
1994
Simul. Pract. Theory, 1994
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994
Matrix multiplication on the MasPar using distance insensitive communication schemes.
Proceedings of the International Symposium on Parallel Architectures, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
Scheduling Policies for Fault Tolerance in a VLSI Processor.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
On Soft Switch Programming for Reconfigurable Array Systems.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements.
IEEE Trans. Very Large Scale Integr. Syst., 1993
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993
On the Methods to Detect Sector Faults of a Disk Subsystem.
Proceedings of the MASCOTS '93, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Proceedings of the European Design Automation Conference 1993, 1993
On the Reconfigurable Operation of Arrays with Defects for Image Processing.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Detection of Defective Media in Disks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Evaluation and improvement of fault coverage of conformance testing by UIO sequences.
IEEE Trans. Commun., 1992
IEEE Trans. Computers, 1992
A data path approach for testing microprocessors with a fault bound: the MC68000 case.
Microprocess. Microsystems, 1992
J. Electron. Test., 1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
On the Verification and Validation of Protocols with High Fault Coverage Using UIO Sequences.
Proceedings of the 11th Symposium on Reliable Distributed Systems, 1992
1991
Microprocessing and Microprogramming, 1991
On a new approach for enhancing the fault coverage of conformance testing of protocols.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991
Protocol Conformance Testing by Discriminating UIO Sequences.
Proceedings of the Protocol Specification, 1991
1990
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
IEEE Trans. Computers, 1990
IEEE Trans. Computers, 1990
Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection.
J. Electron. Test., 1990
Evaluation and improvement of fault coverage for verification and validation of protocols.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990
A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
Microprocess. Microsystems, 1989
Microprocess. Microprogramming, 1989
Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement.
Proceedings of the Proceedings International Test Conference 1989, 1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
Proceedings of the 9th Symposium on Computer Arithmetic, 1989
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
Microprocess. Microprogramming, 1988
Comput. J., 1988
New Approaches for the Reconfiguration of Two-Dimensional VLSI Arrays Using Time-Redundancy.
Proceedings of the 9th IEEE Real-Time Systems Symposium (RTSS '88), 1988
Array partitioning: a methodology for reconfigurability and reconfiguration problems.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
J. Parallel Distributed Comput., 1987
A Technique for Reconfiguring Two Dimensional VLSI Arrays.
Proceedings of the 8th IEEE Real-Time Systems Symposium (RTSS '87), 1987
1986
An Architecture and an Interconnection Scheme for Time-Sliced Buses in Real-Time Processing.
Proceedings of the 7th IEEE Real-Time Systems Symposium (RTSS '86), 1986
1985
On a Multiprocessor System with Dynamic Redundancy.
Proceedings of the 6th IEEE Real-Time Systems Symposium (RTSS '85), 1985
1984
Investigation and design of a controller of an asynchronous system for fault-tolerant aircraft control using hybrid voting techniques.
Softw. Microsystems, 1984