Fabrizio Ferrandi

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

Towards Automated Generation of Chiplet-Based Systems Invited Paper.

[BibT_eX]

[DOI]

Ankur Limaye

Claudio Barone

Joseph B. Manzano

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.

[BibT_eX]

[DOI]

CoRR, 2023

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms.

[BibT_eX]

[DOI]

CoRR, 2023

TrueFloat: A Templatized Arithmetic Library for HLS Floating-Point Operators.

[BibT_eX]

[DOI]

Michele Fiorito

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Using High-Level Synthesis to model System Verilog procedural timing controls.

[BibT_eX]

[DOI]

Luca Ezio Pozzoni

Loris Mendola

Alfio Antonino Palazzo

Francesco Pappalardo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem.

[BibT_eX]

[DOI]

Vicente Nicolau Gallego

Patricia López Cueva

Jean-noel Letrillard

Franck Wartel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Exploration of Synthesis Methods from Simulink Models to FPGA for Aerospace Applications.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon.

[BibT_eX]

[DOI]

Ankur Limaye

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

From High-Level Frameworks to custom Silicon with SODA.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited.

[BibT_eX]

[DOI]

Joseph B. Manzano

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Hardware acceleration of complex machine learning models through modern high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

MLIR Loop Optimizations for High-Level Synthesis: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021

Automatic Generation of Heterogeneous SoC Architectures With Secure Communications.

[BibT_eX]

[DOI]

Mattia Tibaldi

IEEE Embed. Syst. Lett., 2021

De-specializing an HLS library for Deep Neural Networks: improvements upon hls4ml.

[BibT_eX]

[DOI]

CoRR, 2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Parametric Throughput Oriented Large Integer Multipliers for High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms.

[BibT_eX]

[DOI]

Dionysios Diamantopoulos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications.

[BibT_eX]

[DOI]

ACM Trans. Parallel Comput., 2020

Tensor Optimization for High-Level Synthesis Design Flows.

[BibT_eX]

[DOI]

Marco Siracusa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

Software defined architectures for data analytics.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems.

[BibT_eX]

[DOI]

Maxime Perrotin

IEEE Trans. Multi Scale Comput. Syst., 2018

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

2017

Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

Exploiting vectorization in high level synthesis of nested irregular loops.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Performance Estimation of Task Graphs Based on Path Profiling.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2016

Efficient synthesis of graph methods: a dynamically scheduled architecture.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A dynamically scheduled architecture for the synthesis of graph methods.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Enabling the high level synthesis of data analytics accelerators.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015

Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

Trace-based automated logical debugging for high-level synthesis generated circuits.

[BibT_eX]

[DOI]

Michele Castellana

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Code Transformations Based on Speculative SDC Scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

High Level Synthesis of RDF Queries for Graph Analytics.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Inter-procedural resource sharing in High Level Synthesis through function proxies.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Function Proxies for Improved Resource Sharing in High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Exploiting Outer Loops Vectorization in High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014

High-level synthesis of memory bound and irregular parallel applications with Bambu.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Modeling pipelined application with Synchronous Data Flow graphs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Harnessing Adaptivity Analysis for the Automatic Design of Efficient Embedded and HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Applications Acceleration through Adaptive Hardware Components.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Dynamic AC-scheduling for hardware cores with unknown and uncertain information.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

An automated flow for the High Level Synthesis of coarse grained parallel applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Bambu: A modular framework for the high level synthesis of memory-intensive applications.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Scheduling independent liveness analysis for register binding in high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012

Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Instructions activating conditions for hardware-based auto-scheduling.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, CF'12, 2012

Performance estimation of embedded software with confidence levels.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A design methodology for the automatic sizing of standard-cell libraries.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A design methodology to implement memory accesses in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Evaluating Static CMOS Complex Cells in Technology Mapping.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

A runtime adaptive controller for supporting hardware components with variable latency.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.

[BibT_eX]

[DOI]

José Gabriel F. Coutinho

IEEE Micro, 2010

Fine grain analysis of simulators accuracy for calibrating performance models.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation.

[BibT_eX]

[DOI]

Proceedings of the Genetic and Evolutionary Computation Conference, 2010

A reconfigurable multiprocessor architecture for a reliable face recognition implementation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Performance modeling of embedded applications with zero architectural knowledge.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009

Performance estimation for task graphs combining sequential path profiling and control dependence regions.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Performance modeling of parallel applications on MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

hArtes design flow for heterogeneous platforms.

[BibT_eX]

[DOI]

Muhammad Rashid

Koen Bertels

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A multiprocessor self-reconfigurable JPEG2000 encoder.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Genetic and Evolutionary Computation Conference, 2009

HW/SW methodologies for synchronization in FPGA multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Improving evolutionary exploration to area-time optimization of FPGA designs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2008

Lightweight DMA management mechanisms for multiprocessors on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

A layout-similarity-based approach for detecting phishing pages.

[BibT_eX]

[DOI]

Angelo P. E. Rosiello

Engin Kirda

Christopher Kruegel

Proceedings of the Third International Conference on Security and Privacy in Communication Networks and the Workshops, 2007

An Interrupt Controller for FPGA-based Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

An Evolutionary Approach to Area-Time Optimization of FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis.

[BibT_eX]

[DOI]

Angelo P. E. Rosiello

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A design kit for a fully working shared memory multiprocessor on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Fitness inheritance in evolutionary and multi-objective high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2007

A Self-Reconfigurable Implementation of the JPEG Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Automatic Test Pattern Generation with BOA.

[BibT_eX]

[DOI]

Proceedings of the Parallel Problem Solving from Nature, 2006

Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead.

[BibT_eX]

[DOI]

Marco Novati

Massimo Morandi

Proceedings of the International Symposium on System-on-Chip, 2006

VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A SystemC-based Framework of Communication Architecture.

[BibT_eX]

[DOI]

Francesco Bruschi

Proceedings of the Forum on specification and Design Languages, 2006

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture.

[BibT_eX]

Carlo Amicucci

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Using speculative computation and parallelizing techniques to improve scheduling of control based designs.

[BibT_eX]

[DOI]

Roberto Cordone

Gianluca Palermo

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A Framework for the Functional Verification of SystemC Models.

[BibT_eX]

[DOI]

Francesco Bruschi

Int. J. Parallel Program., 2005

Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.

[BibT_eX]

[DOI]

Alberto Donato

Massimo Redaelli

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Operating system support for dynamically reconfigurable SoC architectures.

[BibT_eX]

[DOI]

Alberto Donato

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms.

[BibT_eX]

[DOI]

Alberto Donato

Massimo Redaelli

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004

System Level Hardware-Software Design Exploration with XCS.

[BibT_eX]

[DOI]

Pier Luca Lanzi

Proceedings of the Genetic and Evolutionary Computation, 2004

System-level metrics for hardware/software architectural mapping.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Identification of design errors through functional testing.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

Synthesis of Complex Control Structures from Behavioral SystemC Models.

[BibT_eX]

[DOI]

Francesco Bruschi

Proceedings of the 2003 Design, 2003

Mining interesting patterns from hardware-software codesign data with the learning classifier system XCS.

[BibT_eX]

[DOI]

Pier Luca Lanzi

Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002

Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications.

[BibT_eX]

[DOI]

Franco Fummi

IEEE Trans. Computers, 2002

Behavioral test generation for the selection of BIST logic.

[BibT_eX]

[DOI]

J. Syst. Archit., 2002

Functional Verification for SystemC Descriptions Using Constraint Solving.

[BibT_eX]

[DOI]

Michele Rendine

Proceedings of the 2002 Design, 2002

Error Simulation Based on the SystemC Design Description Language.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

An efficient heuristic approach to solve the unate covering problem.

[BibT_eX]

[DOI]

Roberto Cordone

Roberto Wolfler Calvo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Semiconcurrent Error Detection in Data Paths.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

Functional test generation for behaviorally sequential models.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Symbolic optimization of interacting controllers based onredundancy identification and removal.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Testability Alternatives Exploration through Functional Testing.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An Application of Genetic Algorithms and BDDs to Functional Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An approach to functional testing of VLIW architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

BIST Architectures Selection Based on Behavioral Testing.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999

Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Symbolic Functional Vector Generation for VHDL Specifications.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Implicit test generation for behavioral VHDL models.

[BibT_eX]

[DOI]

Franco Fummi

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Automatic VHDL restructuring for RTL synthesis optimization and testability improvement.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Power Estimation of Behavioral Descriptions.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Testing Core-Based Systems: A Symbolic Methodology.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1997

Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

How an "Evolving" Fault Model Improves the Behavioral Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Property verification in the design of telecom applications.

[BibT_eX]

[DOI]

Massimo Bombana

Patrizia Cavalloro

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Implicit Test Sequences Compaction for Decreasing Test Application Cos.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

BDD-based testability estimation of VHDL designs.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Data Path Testability Analysis Based on BDDs.

[BibT_eX]

Giacomo Buonanno

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

ALADIN: a multilevel testability analyzer for VLSI system design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Reduction of fault detection costs through a BDD formalism.

[BibT_eX]

[DOI]