Fabrice Muller

According to our database1, Fabrice Muller authored at least 24 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera.
Int. J. Circuit Theory Appl., 2018

2015
FoRTReSS: a flow for design space exploration of partially reconfigurable systems.
Des. Autom. Embed. Syst., 2015

An energy-aware scheduler for dynamically reconfigurable multi-core systems.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

2013
Méthodologie dédiée aux applications parallèles sur plateforme reconfigurable dynamiquement.
Tech. Sci. Informatiques, 2013

Online codesign on reconfigurable platform for parallel computing.
Microprocess. Microsystems, 2013

Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM.
Microprocess. Microsystems, 2013

Design space exploration for partially reconfigurable architectures in real-time systems.
J. Syst. Archit., 2013

Complete and Approximate Methods for Off-Line Placement of Hardware Tasks on Reconfigurable Devices.
J. Circuits Syst. Comput., 2013

2012
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model.
IET Comput. Digit. Tech., 2012

Fast integration of hardware accelerators for dynamically reconfigurable architecture.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

2011
Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices.
Int. J. Reconfigurable Comput., 2011

Schedulers-Driven approach for dynamic placement/scheduling of multiple DAGs onto SoPCs.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Placement of Hardware Tasks on FPGA using the Bees Algorithm.
Proceedings of the PECCS 2011, 2011

Methodology for designing partially reconfigurable systems using transaction-level modeling.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Architectures multiprocesseurs, distribuées et reconfigurables dynamiquement pour les applications temps réel.
, 2011

2010
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA.
Int. J. Reconfigurable Comput., 2010

New Three-level Resource Management for Off-line Placement of Hardware Tasks on Reconfigurable Devices.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

2009
Off-line placement of hardware tasks on FPGA.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Weight Bound Limits in Supertasking Approach for Guaranteed Timeline Constraints.
Proceedings of the 37th International Conference on Parallel Processing, 2008

2006
FPGA-based generic neural network architecture.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

2001
Computer-Supported Deliberations for Distributed Teams.
Proceedings of the Innovative Internet Computing Systems, 2001

A Generic Support for Distributed Deliberations.
Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001


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