Fábio Luís Livi Ramos

According to our database1, Fábio Luís Livi Ramos authored at least 16 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Statistical Analysis of VVC Residual and Entropy Coding aiming Efficient Hardware Design.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Analysis of AV1 Arithmetic Decoder Design Space with a Novel Multi-Boolean Approach.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

2022
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder.
IEEE Des. Test, 2022

Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture.
IEEE Des. Test, 2022

Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding.
Proceedings of the Picture Coding Symposium, 2022

Power-Throughput Trade-off Analysis for a Novel Multi-Boolean AV1 Arithmetic Encoder Design.
Proceedings of the Picture Coding Symposium, 2022

2021
Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2021

2020
Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2018
High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-power multi-size HEVC DCT architecture proposal for QFHD video processing.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2010
A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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