Fabien Clermidy
According to our database1,
Fabien Clermidy
authored at least 96 papers
between 1999 and 2023.
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Bibliography
2023
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration.
IEEE J. Solid State Circuits, 2023
2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021
2020
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2017
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits.
Microelectron. J., 2017
IEEE Micro, 2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Emerging resistive memories for low power embedded applications and neuromorphic systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A Co-design Approach for Hardware Optimizations in Multicore Architectures Using MCAPI.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
J. Parallel Distributed Comput., 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method.
ACM J. Emerg. Technol. Comput. Syst., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chip.
Proceedings of the NOCS 2011, 2011
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
A low complexity stopping criterion for reducing power consumption in turbo decoders.
Proceedings of the Design, Automation and Test in Europe, 2011
Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
J. Low Power Electron., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms.
Proceedings of the NOCS 2010, 2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Power consumption analysis and energy efficient optimization for turbo decoder implementation.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
A Communication and configuration controller for NoC based reconfigurable data flow architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
IEEE J. Solid State Circuits, 2008
Int. J. Reconfigurable Comput., 2008
Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.
Proceedings of the ESSCIRC 2008, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A Comparison between NoC and Bus Architectures Based on a Real-Application.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
1999
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999