Fabian Olivera

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2022

Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node.

[BibT_eX]

[DOI]

Lucas Souza da Silva

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021

A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design.

[BibT_eX]

[DOI]

Lucas Souza da Silva

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Three-Stage Charge Pump With Forward Body Biasing in 28 nm UTBB FD-SOI CMOS.

[BibT_eX]

[DOI]

Carlos A. Pinheiro

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Closed-Form Analysis of Metastability Voltage in 28-nm UTBB FD-SOI CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Adjustable Output CMOS Voltage Reference Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2018

Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology.

[BibT_eX]

[DOI]

Microelectron. J., 2018

2017

Analytic modeling of static noise margin considering DIBL and body bias effects.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Analytic boundaries for 6T-SRAM design in standby mode.

[BibT_eX]

[DOI]

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2015

A computer-aided approach for voltage reference circuit design.

[BibT_eX]

[DOI]