F. Schleicher

According to our database, F. Schleicher authored at least 2 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias.

P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022