F. Jesús Sánchez

Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006

Instruction scheduling for a clustered VLIW processor with a word-interleaved cache.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2006

2005

Distributed Data Cache Designs for Clustered VLIW Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices.

[BibT_eX]

[DOI]

Carlos García Quiñones

Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

The Mitosis Speculative Multithreaded Architectures.

[BibT_eX]

Carlos Madriles

Carlos García Quiñones

Pedro Marcuello

Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

Variable-Based Multi-module Data Caches for Clustered VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2003

Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002

Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

An interleaved cache clustered VLIW processor.

[BibT_eX]

[DOI]

Proceedings of the 16th international conference on Supercomputing, 2002

Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache .

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2001

Graph-partitioning based instruction scheduling for clustered processors.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.

[BibT_eX]

[DOI]

Josep M. Codina

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000

Analyzing Data Locality in Numeric Applications.

[BibT_eX]

[DOI]

IEEE Micro, 2000

Modulo scheduling for a fully-distributed clustered VLIW architecture.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Instruction Scheduling for Clustered VLIW Architectures.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Parallel Processing, 2000

1999

Software Data Prefetching for Software Pipelined Loops.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1999

A locality sensitive multi-module cache with explicit management.

[BibT_eX]

[DOI]

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Software Prefetching for Software Pipelined Loops.

[BibT_eX]

[DOI]

Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

Fast, Accurate and Flexible Data Locality Analysis.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997

Cache Sensitive Modulo Scheduling.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Static Locality Analysis for Cache Management.

[BibT_eX]

[DOI]