Eunchong Lee

Orcid: 0000-0001-7873-2920

According to our database1, Eunchong Lee authored at least 18 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Strategic Improvements in CNN Accelerators: Optimizing PE Utilization for MobileNetV2.
Proceedings of the 21st International SoC Design Conference, 2024

A Simple Up-and-Down Weight Update Method for Tiny 8-bit Quantized CNN Training.
Proceedings of the 21st International SoC Design Conference, 2024

A Fully 4-bit Quantized MobileNet-SSD.
Proceedings of the 21st International SoC Design Conference, 2024

HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Deep Learning Accelerators' Configuration Space Exploration Effect on Performance and Resource Utilization: A Gemmini Case Study.
Sensors, March, 2023

Lightweight and Energy-Efficient Deep Learning Accelerator for Real-Time Object Detection on Edge Devices.
Sensors, February, 2023

A Max Pooling Hardware Architecture Supporting Inference And Training For CNN Accelerators.
Proceedings of the 20th International SoC Design Conference, 2023

An Efficient NPU-Aware Filter Pruning in Convolutional Neural Network.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022
Exploring GEMM Operations on Different Configurations of the Gemmini Accelerator.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Memory-Centric Architecture of Neural Processing Unit for Edge Device.
Proceedings of the 18th International SoC Design Conference, 2021

2020
Implementation of a Round Robin Processing Element for Deep Learning Accelerator.
Proceedings of the International SoC Design Conference, 2020

2019
An Implementation of the System on Chip Control System for a FPGA-Based Computer Vision Accelerator.
Proceedings of the 2019 International SoC Design Conference, 2019

FPGA Design and Implementation of Accelerated Stereo Matching for Obstacle Detection.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018
System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles.
Proceedings of the International SoC Design Conference, 2018

2016
Hardware implementation of fast high dynamic range processor for real-time 4K UHD video.
Proceedings of the International SoC Design Conference, 2016

Hardware implementation of fast traffic sign recognition for intelligent vehicle system.
Proceedings of the International SoC Design Conference, 2016

2015
Various Threat Models to Circumvent Air-Gapped Systems for Preventing Network Attack.
Proceedings of the Information Security Applications - 16th International Workshop, 2015

2013
An implementation of intra prediction with transform for H.264/AVC.
IEICE Electron. Express, 2013


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