Eun Sei Park

According to our database, Eun Sei Park authored at least 8 papers between 1988 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits.

Byunggyu Kwak, Eun Sei Park

Proceedings of the 35th Conference on Design Automation, 1998

1995

Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs.

Sung Tae Jung, Eun Sei Park, Jung Sik Kim, Chu Shik Jhon

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993

Switch-Level ATPG Using Constraint-Guided Line Justification.

Eun Sei Park, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

An efficient delay test generation system for combinational logic circuits.

Eun Sei Park, M. Ray Mercer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

The Total Delay Fault Model and Statistical Delay Fault Coverage.

Eun Sei Park, M. Ray Mercer, Thomas W. Williams

IEEE Trans. Computers, 1992

1991

Delay Testing Quality in Timing-Optimized Designs.

Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1989

A statistical model for delay-fault testing.

Eun Sei Park, M. Ray Mercer, Thomas W. Williams

IEEE Des. Test, 1989

1988

Statistical Delay Fault Coverage and Defect Level for Delay Faults.

Eun Sei Park, Thomas W. Williams, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1988, 1988