Eui-Young Chung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Auto Batching Scheme for Optimizing LSTM Inference on FPGA Platforms.

[BibT_eX]

[DOI]

Byoung Jin Kim

IEEE Access, 2024

2023

Unified Wear-Leveling Technique for NVM-Based Buffer of SSD.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Operand-Oriented Virtual Memory Support for Near-Memory Processing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, August, 2023

Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Developing a Job Search Platform for SMEs to Resolve Job Mismatch: A Case Study.

[BibT_eX]

[DOI]

Junghwan Lee

Dongwook Kim

Int. J. Asian Bus. Inf. Manag., 2023

Adaptive Tag Comparison for Hybrid Cache.

[BibT_eX]

[DOI]

Seong Jae Eom

Proceedings of the 20th International SoC Design Conference, 2023

2022

STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2021

Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection.

[BibT_eX]

[DOI]

Yun-Seok Oh

IEEE Access, 2021

Cross-Corner Delay Variation Model for Standard Cell Libraries.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

Multitoken-Based Power Management for NAND Flash Storage Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

The necessity of anterior knowledge exchange activities for technological collaboration and innovation performance improvement.

[BibT_eX]

[DOI]

Kibaek Lee

Int. J. Technol. Manag., 2020

Exploring Replacement Policy for Memcached.

[BibT_eX]

[DOI]

Gi Lee

Byoung Jin Kim

Proceedings of the International SoC Design Conference, 2020

Resource Utilization Optimized Design Method for Matched Filter of PSS Searcher.

[BibT_eX]

[DOI]

Dohyun Kim

Taeyang Jeong

Proceedings of the International SoC Design Conference, 2020

A Fast Full-System Simulation Environment for Memory System Evaluation.

[BibT_eX]

[DOI]

Taeyang Jeong

Sangwoo Han

Proceedings of the International SoC Design Conference, 2020

Asymmetric Prefetching Architecture for Multicore Processor.

[BibT_eX]

[DOI]

Duheon Choi

Kwangsu Kim

Proceedings of the International SoC Design Conference, 2020

2019

A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning.

[BibT_eX]

[DOI]

Byunghoon Lee

Kwangsu Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Asymmetric Slew Logic Threshold Method on Near Threshold Region.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Software and Computer Applications, 2018

CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA.

[BibT_eX]

[DOI]

Jeongbin Kim

Ki Tae Kim

Proceedings of the 7th International Conference on Software and Computer Applications, 2018

A Study of Data Layout in Multi-channel Processing-In-Memory Architecture.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Software and Computer Applications, 2018

2017

Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

An effective pre-store/pre-load method exploiting intra-request idle time of NAND flash-based storage devices.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Timing window wiper: A new scheme for reducing refresh power of DRAM.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Near-Data Processing for Machine Learning.

[BibT_eX]

[DOI]

CoRR, 2016

FPGA power estimation simulator for dynamic input data.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

A RAM cache approach using host memory buffer of the NVMe interface.

[BibT_eX]

[DOI]

JuHyung Hong

Sangwoo Han

Proceedings of the International SoC Design Conference, 2016

PIM architecture exploration for HMC.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

FRAME: Fast and Realistic Attacker Modeling and Evaluation for Temporal Logical Correlation in Static Noise.

[BibT_eX]

[DOI]

CoRR, 2015

A High-Performance Solid-State Disk with Double-Data-Rate NAND Flash Memory.

[BibT_eX]

[DOI]

CoRR, 2015

2014

An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis.

[BibT_eX]

[DOI]

Won Woo Ro

IEEE Trans. Computers, 2014

Design of a bitmap-based QoS-aware memory controller for a packet memory.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2014

2013

A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method.

[BibT_eX]

[DOI]

Seung-Chul Kim

IEICE Trans. Inf. Syst., 2013

Power Failure Protection Scheme for Reliable High-Performance Solid State Disks.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

Page overwriting method for performance improvement of NAND flash memories.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

GPU-based acceleration of an RNA tertiary structure prediction algorithm.

[BibT_eX]

[DOI]

Comput. Biol. Medicine, 2013

2012

Application-Support Particle Filter for Dynamic Voltage Scaling of Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network.

[BibT_eX]

[DOI]

Deumji Woo

IEEE Trans. Computers, 2012

Analytical memory bandwidth model for many-core processor based systems.

[BibT_eX]

[DOI]

Woo-Cheol Cho

IEICE Electron. Express, 2012

Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture.

[BibT_eX]

[DOI]

Myoung-Jin Kim

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

High-voltage wordline generator for low-power program operation in NAND flash memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Energy-Optimal Dynamic Thermal Management: Computation and Cooling Power Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2010

On the Thermal Attack in Instruction Caches.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2010

Architecture Exploration of High-Performance PCs with a Solid-State Disk.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

A fast and simple system performance emulator for enhanced solid state disks: a case study of long read operations.

[BibT_eX]

[DOI]

J. Zhejiang Univ. Sci. C, 2010

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning.

[BibT_eX]

[DOI]

Comput. J., 2010

Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network.

[BibT_eX]

[DOI]

Sungroh Yoon

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2009

High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation.

[BibT_eX]

[DOI]

Myeongjin Kim

Sungroh Yoon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Topology Synthesis of Cascaded Crossbar Switches.

[BibT_eX]

[DOI]

Sungjoo Yoo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

K-maximin clustering: a maximin correlation approach to partition-based clustering.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2009

A robust peak detection method for RNA structure inference by high-throughput contact mapping.

[BibT_eX]

[DOI]

Bioinform., 2009

Energy-optimal dynamic thermal management for green computing.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Energy and Performance Optimization of Demand Paging With OneNAND Flash.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Extended MPEG Video Format for Efficient Dynamic Voltage Scaling.

[BibT_eX]

[DOI]

Kwanhu Bang

Sung-Yong Bang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.

[BibT_eX]

[DOI]

Cheol Hong Kim

Sung Woo Chung

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.

[BibT_eX]

[DOI]

Sungjoo Yoo

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Latency-Aware Bus Arbitration for Real-Time Embedded Systems.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis.

[BibT_eX]

[DOI]

Sung Woo Chung

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Clustering protein environments for function prediction: finding PROSITE motifs in 3D.

[BibT_eX]

[DOI]

BMC Bioinform., 2007

Is the Complicated ECC Array Necessary for Data Caches?

[BibT_eX]

Proceedings of the 2007 International Conference on Computer Design, 2007

Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Exploiting Binary Abstractions in Deciphering Gene Interactions.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006

Demand paging for OneNAND<sup>TM</sup> Flash eXecute-in-place.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Worst case execution time analysis for synthesized hardware.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

PowerV<i>i</i>P: Soc power estimation framework at transaction level.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2002

Value-sensitive automatic code specialization for embedded software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Dynamic Power Management for Nonstationary Service Requests.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Contents provider-assisted dynamic voltage scaling for low energy multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

Source code transformation based on software cost analysis.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Automatic source code specialization for energy reduction.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Quantitative Comparison of Power Management Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Dynamic power management using adaptive learning tree.

[BibT_eX]

[DOI]