Euhan Chong
Orcid: 0000-0003-0434-4882
According to our database1,
Euhan Chong
authored at least 6 papers
between 2005 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2019
IEEE J. Solid State Circuits, 2019
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005