Euhan Chong

According to our database, Euhan Chong authored at least 6 papers between 2005 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.

Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET.

Euhan Chong, Faisal Ahmed Musa, Ahmed N. Mustafa, Tim Gao, Peter Krotnev, Rashid Soreefan, Qian Xin, Paul Madeira, Davide Tonietto

Proceedings of the 47th ESSCIRC 2021, 2021

2019

A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET.

Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone

IEEE J. Solid State Circuits, 2019

A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.

Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho, Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET.

Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2005

A 400Mbps CMOS spatially-modulated photoreceiver for optical storage.

Euhan Chong, Khoman Phang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005