Ettore Tiotto

Orcid: 0000-0001-5235-8248

According to our database1, Ettore Tiotto authored at least 18 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Experiences Building an MLIR-Based SYCL Compiler.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023
Leveraging MLIR for Better SYCL Compilation (Poster).
Proceedings of the 2023 International Workshop on OpenCL, 2023

2020
OpenMP 4.5 compiler optimization for GPU offloading.
IBM J. Res. Dev., 2020

2019
Memory-access-aware Safety and Profitability Analysis for Transformation of Accelerator-bound OpenMP Loops.
ACM Trans. Archit. Code Optim., 2019

Performance evaluation of OpenMP's target construct on GPUs - exploring compiler optimisations.
Int. J. High Perform. Comput. Netw., 2019

Toward an Analytical Performance Model to Select between GPU and CPU Execution.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
Run-Length Base-Delta Encoding for High-Speed Compression.
Proceedings of the 47th International Conference on Parallel Processing, 2018

Compiler-driven performance workshop.
Proceedings of the 28th Annual International Conference on Computer Science and Software Engineering, 2018

2016
Combining Static and Dynamic Data Coalescing in Unified Parallel C.
IEEE Trans. Parallel Distributed Syst., 2016

Using shared-data localization to reduce the cost of inspector-execution in unified-parallel-C programs.
Parallel Comput., 2016

Exploring Compiler Optimization Opportunities for the OpenMP 4.× Accelerator Model on a POWER8+GPU Platform.
Proceedings of the Third Workshop on Accelerator Programming Using Directives, 2016

2015
14th compiler-driven performance workshop.
Proceedings of 25th Annual International Conference on Computer Science and Software Engineering, 2015

2014
Reducing Compiler-Inserted Instrumentation in Unified-Parallel-C Code Generation.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Memory Management Techniques for Exploiting RDMA in PGAS Languages.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

2013
Improving performance of all-to-all communication through loop scheduling in PGAS environments.
Proceedings of the International Conference on Supercomputing, 2013

Improving communication in PGAS environments: static and dynamic coalescing in UPC.
Proceedings of the International Conference on Supercomputing, 2013

2012
Automatic communication coalescing for irregular computations in UPC language.
Proceedings of the Center for Advanced Studies on Collaborative Research, 2012

2008
OpenMP tasks in IBM XL compilers.
Proceedings of the 2008 conference of the Centre for Advanced Studies on Collaborative Research, 2008


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