Esteve Amat

Orcid: 0000-0001-9214-0331

According to our database1, Esteve Amat authored at least 17 papers between 2012 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2018
Modem Gain-Cell Memories in Advanced Technologies.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Quantum dot location relevance into SET-FET circuits based on FinFET devices.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
RRAM variability and its mitigation schemes.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Monitoring SRAM BTI degradation by current-based tracking technique.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memories.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Memristive crossbar design and test in non-adaptive proactive reconfiguring scheme.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Statistical lifetime analysis of memristive crossbar matrix.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
A single event transient hardening circuit design technique based on strengthening.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Reliability study on technology trends beyond 20nm.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Analysis of FinFET technology on memories.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012


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