Erl-Huei Lu
According to our database1,
Erl-Huei Lu
authored at least 36 papers
between 1988 and 2018.
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Bibliography
2018
Int. J. Netw. Secur., 2018
2017
An Efficient Weighted Bit-Flipping Algorithm for Decoding LDPC Codes Based on Log-Likelihood Ratio of Bit Error Probability.
IEICE Trans. Commun., 2017
2016
2014
Modifying the ECC-Based Grouping-Proof RFID System to Increase Inpatient Medication Safety.
J. Medical Syst., 2014
IEEE Commun. Lett., 2014
2013
Proceedings of the International Symposium on Wireless and pervasive Computing, 2013
2012
A Mobile RFID-based Mutual Authentication Protocol using Elliptic Curve Cryptography for Security Patrolling Application.
Proceedings of the Radio Frequency Identification System Security, 2012
2011
Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2<sup>m</sup>).
Int. J. Auton. Adapt. Commun. Syst., 2011
2010
Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder.
IEICE Trans. Commun., 2010
2009
Proceedings of the Advances in Information Security and Assurance, 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2<sup>m</sup>).
Proceedings of the 5th International Conference on Mobile Technology, 2008
2006
Comput. Commun., 2006
Proceedings of the IEEE International Conference on Sensor Networks, 2006
Proceedings of the IEEE International Conference on Systems, 2006
2005
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2<sup>m</sup>).
IEEE Trans. Computers, 2005
Ringed bit-parallel systolic multipliers over a class of fields GF(2<sup><i>m</i></sup>).
Integr., 2005
Appl. Math. Comput., 2005
ID-based threshold digital signature schemes on the elliptic curve discrete logarithm problem.
Appl. Math. Comput., 2005
Appl. Math. Comput., 2005
2004
Low complexity bit-parallel systolic architecture for computing <i>C+AB</i><sup>2</sup> over a class of GF(2<sup><i>m</i></sup>).
Integr., 2004
2002
Dynamic reblocking RSA-based multisignatures scheme for computer and communication networks.
IEEE Commun. Lett., 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.
IEEE Trans. Computers, 2001
Inf. Process. Lett., 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
1998
Inf. Process. Lett., 1998
1994
Corrigendum: A Complete Decoding Algorithm for Double-Error-Correcting Primitive Binary BCH Codes of Odd m.
Inf. Process. Lett., 1994
A Complete Decoding Algorithm for Double-Error-Correcting Primitive Binary BCH Codes of Odd m.
Inf. Process. Lett., 1994
1988
A programmable VLSI architecture for computing multiplication and polynomial evaluation modulo a positive integer.
IEEE J. Solid State Circuits, February, 1988
Proceedings of the Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?, 1988