Erkan Diken

According to our database1, Erkan Diken authored at least 13 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2018
An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

2016
A configurable SIMD architecture with explicit datapath for intelligent learning.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015
A compilation technique and performance profits for VLIW with heterogeneous vectors.
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths.
Microprocess. Microsystems, 2014

Construction and exploitation of VLIW asips with multiple vector-widths.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocess. Microsystems, 2013

Rapid and accurate energy estimation of vector processing in VLIW ASIPs.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

2012
ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips.
Int. J. Reconfigurable Comput., 2011

2010
A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010


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