Eriko Nurvitadhi

Vaughn Betz

IEEE Access, 2022

RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices.

[BibT_eX]

[DOI]

Andrew Boutros

Vaughn Betz

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

Specializing FGPU for Persistent Deep Learning.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2021

Enhancing High-Level Synthesis Using a Meta-Programming Approach.

[BibT_eX]

[DOI]

José Gabriel de Figueiredo Coutinho

IEEE Trans. Computers, 2021

FlexScore: Quantifying Flexibility.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

Cache Compression with Efficient in-SRAM Data Comparison.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

Specializing for Efficiency: Customizing AI Inference Processors on FPGAs.

[BibT_eX]

[DOI]

Andrew Boutros

Shreyas K. Venkataramanaiah

Vaughn Betz

Proceedings of the International Conference on Microelectronics, 2021

DO-GPU: Domain Optimizable Soft GPUs.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.

[BibT_eX]

[DOI]

Anupreetham Anupreetham

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Stratix 10 NX Architecture and Applications.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies.

[BibT_eX]

[DOI]

José Gabriel F. Coutinho

Tim Todman

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Optimizing Reconfigurable Recurrent Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SLATE: Managing Heterogeneous Cloud Functions.

[BibT_eX]

[DOI]

José Gabriel F. Coutinho

Mishali Naik

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Dark Wires and the Opportunities for Reconfigurable Logic.

[BibT_eX]

[DOI]

Tian Tan

Derek Chiou

IEEE Comput. Archit. Lett., 2019

FPGA-based Computing in the Era of AI and Big Data.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity.

[BibT_eX]

[DOI]

José Gabriel F. Coutinho

Shreyas Kolala Venkataramanaiah

Mishali Naik

Proceedings of the International Conference on Field-Programmable Technology, 2019

Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Automatic Compiler Based FPGA Accelerator for CNN Training.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform.

[BibT_eX]

[DOI]

Yu Wang

James C. Hoe

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs.

[BibT_eX]

[DOI]

CoRR, 2018

WRPN: Wide Reduced-Precision Networks.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Learning Representations, 2018

Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

WRPN: Training and Inference using Wide Reduced-Precision Networks.

[BibT_eX]

[DOI]

CoRR, 2017

Accelerating Deep Convolutional Networks using low-precision and sparsity.

[BibT_eX]

[DOI]

Ganesh Venkatesh

Debbie Marr

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Customizable FPGA OpenCL matrix multiply design template for deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

High performance binary neural networks on the Xeon+FPGA™ platform.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Fine-grained accelerators for sparse machine learning workloads.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming.

[BibT_eX]

[DOI]

Proceedings of the Deep Learning and Convolutional Neural Networks for Medical Image Computing, 2016

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Hardware accelerator for analytics of sparse data.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A sparse matrix vector multiply accelerator for support vector machine.

[BibT_eX]

[DOI]

Asit K. Mishra

Debbie Marr

Proceedings of the 2015 International Conference on Compilers, 2015

2014

GraphGen: An FPGA Framework for Vertex-Centric Graph Computation.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Programmable Automotive Headlights.

[BibT_eX]

[DOI]

Srinivasa G. Narasimhan

Proceedings of the Computer Vision - ECCV 2014, 2014

2013

MEMOCODE 2013 hardware/software co-design contest: Stereo matching.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Hardware-efficient stereo estimation using a residual-based approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2013

3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2013

2011

Automatic Pipelining From Transactional Datapath Specifications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Integrating formal verification and high-level processor pipeline synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

2010

Automatic multithreaded pipeline synthesis from transactional datapath specifications.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2009

2008

Active Cache Emulator.

[BibT_eX]

[DOI]

Jumnit Hong

Shih-Lien Lu

IEEE Trans. Very Large Scale Integr. Syst., 2008

A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007

Adaptive semi-soft handoff for Cellular IP networks.

[BibT_eX]

[DOI]

Int. J. Wirel. Mob. Comput., 2007

PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Design, implementation, and verification of active cache emulator (ACE).

[BibT_eX]

[DOI]

Jumnit Hong

Shih-Lien Lu

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

TRUSS: A Reliable, Scalable Server Architecture.

[BibT_eX]

[DOI]

Vasileios Liaskovitis

IEEE Micro, 2005

Dynamic voltage scaling techniques for power efficient video decoding.

[BibT_eX]

[DOI]

J. Syst. Archit., 2005

Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C.

[BibT_eX]

[DOI]