Érika F. Cota

Orcid: 0000-0001-7431-7738

Affiliations:
  • Federal University of Rio Grande do Sul, Porto Alegre, Brazil


According to our database1, Érika F. Cota authored at least 63 papers between 1997 and 2022.

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Bibliography

2022
Mobilex: a generic framework for cross-platform mobile development based on web language.
Proceedings of the SBES 2022: XXXVI Brazilian Symposium on Software Engineering, Virtual Event Brazil, October 5, 2022

2021
ExecutionFlow: a tool to compute test paths of Java methods and constructors.
Proceedings of the 35th Brazilian Symposium on Software Engineering, 2021

2020
Use case evolution analysis based on graph transformation with negative application conditions.
Sci. Comput. Program., 2020

Predicting Prime Path Coverage Using Regression Analysis.
Proceedings of the 34th Brazilian Symposium on Software Engineering, 2020

2019
Supporting BPMN tool developers through meta-algorithms.
Int. J. Bus. Inf. Syst., 2019

2018
EPE-Mobile - A framework for early performance estimation of mobile applications.
Softw. Pract. Exp., 2018

2017
Using formal methods for content validation of medical procedure documents.
Int. J. Medical Informatics, 2017

2015
Formal Verification of Health Assessment Tools: a Case Study.
Proceedings of the Third Workshop-School on Theoretical Computer Science, 2015

NFRs early estimation through software metrics.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Use Case Analysis Based on Formal Methods: An Empirical Study.
Proceedings of the Recent Trends in Algebraic Development Techniques, 2014

Early Estimation of NFRs for Embedded System Using Design Metrics.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

Performance Evaluation of Android Applications: A Case Study.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

Using Software Metrics to Estimate the Impact of Maintenance in the Performance of Embedded Software.
Proceedings of the 30th IEEE International Conference on Software Maintenance and Evolution, Victoria, BC, Canada, September 29, 2014

2013
Specification of Models Based on Contexts using Graph Grammars.
Proceedings of the 2nd Workshop-School on Theoretical Computer Science, 2013

2011
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing.
J. Parallel Distributed Comput., 2011

Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.
J. Electron. Test., 2011

2010
Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A broad strategy to detect crosstalk faults in network-on-chip interconnects.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

An evaluation of free/open source static analysis tools applied to embedded software.
Proceedings of the 11th Latin American Test Workshop, 2010

Concurrent test of Network-on-Chip interconnects and routers.
Proceedings of the 11th Latin American Test Workshop, 2010

Efficiently using data splitting and retransmission to tolerate faults in networks-on-chip interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Embedded software testing: What kind of problem is this?
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Resource-and-time-aware test strategy for configurable quaternary logic blocks.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Diagnosis of interconnect shorts in mesh NoCs.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time.
Proceedings of the 10th Latin American Test Workshop, 2009

Testing requirements for an embedded operating system: The exception handling case study.
Proceedings of the 10th Latin American Test Workshop, 2009

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers, 2008

Improving the Test of NoC-Based SoCs with Help of Compression Schemes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A fault-tolerant, DFA-resistant AES core.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Crosstalk- and SEU-Aware Networks on Chips.
IEEE Des. Test Comput., 2007

Analysis of the use of declarative languages for enhanced embedded system software development.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Redefining and testing interconnect faults in Mesh NoCs.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Constraint-Driven Test Scheduling for NoC-Based Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A cryptography core tolerant to DFA fault attacks.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Evaluation of SEU and crosstalk effects in network-on-chip switches.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk.
Proceedings of the 2006 IEEE International Test Conference, 2006

Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A constraint-based solution for on-line testing of processors embedded in real-time applications.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

A scalable test strategy for network-on-chip routers.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Reusing an on-chip network for the test of core-based systems.
ACM Trans. Design Autom. Electr. Syst., 2004

Searching for Global Test Costs Optimization in Core-Based Systems.
J. Electron. Test., 2004

Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Reducing test time with processor reuse in network-on-chip based systems.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
The Impact of NoC Reuse on the Testing of Core-based Systems.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Power-aware NoC Reuse on the Testing of Core-based Systems.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Generic and Detailed Search for TAM Definition in Core-Based Systems.
Proceedings of the 3rd Latin American Test Workshop, 2002

Test Planning and Design Space Exploration in a Core-Based Environment.
Proceedings of the 2002 Design, 2002

2001
Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.
J. Electron. Test., 2001

A Test Method for a Broad Class of DSP Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001

2000
A new adaptive analog test and diagnosis system.
IEEE Trans. Instrum. Meas., 2000

Designing a Radiation Hardened 8051-Like Micro-Controller.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Synthesis of a 8051-Like Microcontroller Tolerant to Transient Faults.
Proceedings of the 1st Latin American Test Workshop, 2000

On the Temperature Dependencies of Analog BIST.
Proceedings of the 1st Latin American Test Workshop, 2000

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.
Proceedings of the 2000 Design, 2000

TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Fault modeling of suspended thermal MEMS.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.
Proceedings of the 1999 Design, 1999

1998
Microsystems Testing: an Approach and Open Problems.
Proceedings of the 1998 Design, 1998

1997
A CAT Tool for Frequency-domain Testing and Diagnosis on Analog.
J. Braz. Comput. Soc., 1997


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