Erik R. Altman

Orcid: 0009-0001-0978-0360

Affiliations:
  • Thomas J. Watson Research Center, Yorktown Heights, USA


According to our database1, Erik R. Altman authored at least 77 papers between 1992 and 2024.

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Bibliography

2024
Graph Feature Preprocessor: Real-time Extraction of Subgraph-based Features from Transaction Graphs.
CoRR, 2024

Graph Feature Preprocessor: Real-time Subgraph-based Feature Extraction for Financial Crime Detection.
Proceedings of the 5th ACM International Conference on AI in Finance, 2024

Provably Powerful Graph Neural Networks for Directed Multigraphs.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Realistic Synthetic Financial Transactions for Anti-Money Laundering Models.
CoRR, 2023

Anomaly Detection on IBM Z Mainframes: Performance Analysis and More.
Proceedings of the 16th ACM International Conference on Systems and Storage, 2023

Realistic Synthetic Financial Transactions for Anti-Money Laundering Models.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

2021
Tabular Transformers for Modeling Multivariate Time Series.
Proceedings of the IEEE International Conference on Acoustics, 2021

2019
Synthesizing Credit Card Transactions.
CoRR, 2019

2014
Harsh Chips, but a Grateful Good-Bye.
IEEE Micro, 2014

Patents and High-Speed Datacenter Interconnects.
IEEE Micro, 2014

Big Data and Democratization [Editorial].
IEEE Micro, 2014

Top Picks from 2013.
IEEE Micro, 2014

Reconfigurable Computing, 3D Integration, and Recognizing Leaders in our Field.
IEEE Micro, 2014

Predicting GPU Performance from CPU Runs Using Machine Learning.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Towards an automated approach to use expert systems in the performance testing of distributed systems.
Proceedings of the 2014 Workshop on Joining AcadeMiA and Industry Contributions to Test Automation and Model-Based Testing, 2014

2013
Cool Chips, Mobile Devices, Memory, and IEEE Micro Going Digital.
IEEE Micro, 2013

Dark Silicon and Dangerous Predictions.
IEEE Micro, 2013

Reliability, Theme Issues, and Plagiarism.
IEEE Micro, 2013

Ten Years of Top Picks.
IEEE Micro, 2013

Hot Chips and the Incomplete Job of Exploiting Them.
IEEE Micro, 2013

Preface.
J. Comput. Sci. Technol., 2013

SGB fortifies global SIG community.
Commun. ACM, 2013

The Liquid Metal Blokus Duo Design.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
Hot Interconnects and Hot Topics
IEEE Micro, 2012

Power- and Energy-Aware Computing.
IEEE Micro, 2012

The Odd Couple: Hardware and Software.
IEEE Micro, 2012

Top Picks, Columnists, and Artists.
IEEE Micro, 2012

Micro Evolution.
IEEE Micro, 2012

2011
New Blood, Cool Chips, and Heterogeneous Designs.
IEEE Micro, 2011

CPUs and GPUs: Who Owns the Future?
IEEE Micro, 2011

Big Chips and Beyond.
IEEE Micro, 2011

Very Large-Scale Systems and Some History.
IEEE Micro, 2011

Hot Chips and Remembering a Pioneer.
IEEE Micro, 2011

A Solid Past, A Vital Future.
IEEE Micro, 2011

The language, optimizer, and tools mess.
Proceedings of the CGO 2011, 2011

2010
Observations on tuning a Java enterprise application for performance and scalability.
IBM J. Res. Dev., 2010

Performance analysis of idle programs.
Proceedings of the 25th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2010

2008
08441 Final Report - Emerging Uses and Paradigms for Dynamic Binary Translation.
Proceedings of the Emerging Uses and Paradigms for Dynamic Binary Translation, 26.10., 2008

2007
Efficient Register Mapping and Allocation in LaTTe, an Open-Source Java Just-in-Time Compiler.
IEEE Trans. Parallel Distributed Syst., 2007

2006
Preface.
IBM J. Res. Dev., 2006

2005
Panel Discussion: Architectures for the Future.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

05101 Abstracts Collection - Scheduling for Parallel Architectures: Theory, Applications, Challenges.
Proceedings of the Scheduling for Parallel Architectures: Theory, Applications, Challenges, 2005

05101 Executive Summary - Scheduling for Parallel Architectures: Theory, Applications, Challenges.
Proceedings of the Scheduling for Parallel Architectures: Theory, Applications, Challenges, 2005

2004
<i>V</i>LaTTe: A Java Just-in-Time Compiler for VLIW with Fast Scheduling and Register Allocation.
IEICE Trans. Inf. Syst., 2004

2002
A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors.
Des. Autom. Embed. Syst., 2002

Precise Exception Semantics in Dynamic Compilation.
Proceedings of the Compiler Construction, 11th International Conference, 2002

2001
Dynamic Binary Translation and Optimization.
IEEE Trans. Computers, 2001

Optimization and precise exceptions in dynamic compilation.
SIGARCH Comput. Archit. News, 2001

Workshop on binary translation - 2001.
SIGARCH Comput. Archit. News, 2001

WBT-2000: workshop on binary translation - 2000.
SIGARCH Comput. Archit. News, 2001

Advances and future challenges in binary translation and optimization.
Proc. IEEE, 2001

2000
Reducing virtual call overheads in a Java VM just-in-time compiler.
SIGARCH Comput. Archit. News, 2000

Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory.
Int. J. Parallel Program., 2000

Dynamic and Transparent Binary Translation.
Computer, 2000

Welcome to the Opportunities of Binary Translation.
Computer, 2000

Efficient Java exception handling in just-in-time compilation.
Proceedings of the ACM 2000 Java Grande Conference, San Francisco, CA, USA, 2000

Binary translation and architecture convergence issues for IBM system/390.
Proceedings of the 14th international conference on Supercomputing, 2000

A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Lightweight monitor for Java VM.
SIGARCH Comput. Archit. News, 1999

Optimizations and Oracle Parallelism with Dynamic Translation.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Execution-Based Scheduling for VLIW Architectures.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards.
J. Parallel Distributed Comput., 1998

Optimal Modulo Scheduling Through Enumeration.
Int. J. Parallel Program., 1998

An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

An eight-issue tree-VLIW processor for dynamic binary translation.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
Simulation/evaluation environment for a VLIW processor architecture.
IBM J. Res. Dev., 1997

DAISY: Dynamic Compilation for 100% Architectural Compatibility.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

1996
A Framework for Resource-Constrained Rate-Optimal Software Pipelining.
IEEE Trans. Parallel Distributed Syst., 1996

Co-Scheduling Hardware and Software Pipelines.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

Optimal Software Pipelining Through Enumeration of Schedules.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards.
Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), 1995

An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining.
Proceedings of the Languages and Compilers for Parallel Computing, 1995

1994
Minimizing register requirements under resource-constrained rate-optimal software pipelining.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

A Comparative Study of Multiprocessor List Scheduling Heuristics.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
A Novel Methodology Using Genetic Algorithms for the Design of Caches and Cache Replacement Policy.
Proceedings of the 5th International Conference on Genetic Algorithms, 1993

1992
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs.
Proceedings of the Compiler Construction, 1992


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