Erik H. D'Hollander

Orcid: 0009-0003-3009-7106

Affiliations:
  • Ghent University, Belgium


According to our database1, Erik H. D'Hollander authored at least 54 papers between 1983 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2024
Exploring Large Language Models for Verilog Hardware Design Generation.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

2023
ZyPy: Intercepting NumPy operations for acceleration on FPGAs.
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

2019
Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL.
Algorithms, 2019

Empowering Parallel Computing with Field Programmable Gate Arrays.
Proceedings of the Parallel Computing: Technology Trends, 2019

2018
Heterogeneous Cloud Computing: Design Methodology to Combine Hardware Accelerators.
Proceedings of the 2018 4th International Conference on Cloud Computing Technologies and Applications, 2018

2017
ParaFPGA 2017: Enlarging the Scope of Parallel Programming with FPGAs.
Proceedings of the Parallel Computing is Everywhere, 2017

Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication.
SIGARCH Comput. Archit. News, 2016

2015
ParaFPGA15: Exploring threads and trends in programmable hardware.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

2013
Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools.
Int. J. Reconfigurable Comput., 2013

Performance and Resource Modeling for FPGAs using High-Level Synthesis tools.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

Comparing and combining GPU and FPGA accelerators in an image processing context.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Performance and toolchain of a combined GPU/FPGA desktop (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
Performance and Programming Environment of a Combined GPU/FPGA Desktop.
Proceedings of the Transition of HPC Towards Exascale Computing, 2012

2011
ParaFPGA 2011 - High Performance Computing with Multiple FPGAs: Design Methodology and Applications.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

2009
Efficient memory management for hardware accelerated Java Virtual Machines.
ACM Trans. Design Autom. Electr. Syst., 2009

Refactoring for Data Locality.
Computer, 2009

ParaFPGA: Parallel Computing with Flexible Hardware.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

2008
Refactoring Intermediately Executed Code to Reduce Cache Capacity Misses.
J. Instr. Level Parallelism, 2008

High Performance Computing with FPGAs.
Proceedings of the High Speed and Large Scale Scientific Computing - Selected Papers from the High Performance Computing Workshop, Cetraro, Italy, June 30, 2008

Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.
Trans. High Perform. Embed. Archit. Compil., 2007

Parallel Computing with FPGAs - Concepts and Applications.
Proceedings of the Parallel Computing: Architectures, 2007

2006
Discovery of Locality-Improving Refactorings by Reuse Path Analysis.
Proceedings of the High Performance Computing and Communications, 2006

Intermediately executed code is the key to find refactorings that improve temporal data locality.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Making XML document markup international.
Softw. Pract. Exp., 2005

Generating cache hints for improved program efficiency.
J. Syst. Archit., 2005

RDVIS: A Tool that Visualizes the Causes of Low Locality and Hints Program Optimizations.
Proceedings of the Computational Science, 2005

2004
Using Hammock Graphs to Structure Programs.
IEEE Trans. Software Eng., 2004

Performance Visualizations using XML Representations.
Proceedings of the 8th International Conference on Information Visualisation, 2004

Non-Uniform Dependences Partitioned by Recurrence Chains.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

Platform-Independent Cache Optimization by Pinpointing Low-Locality Reuse.
Proceedings of the Computational Science, 2004

2002
Visualization Enables the Programmer to Reduce Cache Misses.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Reuse Distance-Based Cache Hint Selection.
Proceedings of the Euro-Par 2002, 2002

2001
Loop Parallelization using the 3D Iteration Space Visualizer.
J. Vis. Lang. Comput., 2001

Linear systems and associated problems - introduction.
Parallel Comput., 2001

Visualizing the Impact of the Cache on Program Execution.
Proceedings of the International Conference on Information Visualisation, 2001

2000
Compiler Generated Multithreading to Alleviate Memory Latency.
J. Univers. Comput. Sci., 2000

Partitioning Loops with Variable Dependence Distances.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

Cache Remapping to Improve the Performance of Tiled Algorithms.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
JPT: A Java Parallelization Tool.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1999

1998
The FORTRAN Parallel Transformer and its Programming.
Inf. Sci., 1998

1997
Visualizing the Iteration Space in PEFPT.
Proceedings of the High-Performance Computing and Networking, 1997

1996
PVM Code Generator for the Fortran Parallel Transformer.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1994
Enhancing Parallelism by Removing Cyclic Data Dependencies.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

Extracting the Parallelism in Program with Unstructured Control Statements.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993
Using Hammock Graphs to Eliminate Nonstructured Branch Statements.
Proceedings of the PARLE '93, 1993

Performance Modeling of Microkernel Thread Schedulers for Shared Memory Multiprocessors.
Proceedings of the PARLE '93, 1993

1992
Partitioning and Labeling of Loops by Unimodular Transformations.
IEEE Trans. Parallel Distributed Syst., 1992

1991
Directed Taskgraph Scheduling Using Simulated Annealing.
Proceedings of the International Conference on Parallel Processing, 1991

1989
Partitioning and Labeling of Index Sets in DO Loops with Constant Dependence Vectors.
Proceedings of the International Conference on Parallel Processing, 1989

1987
Implementation of An Automatic Program Partitioner on a Homogeneous Multiprocessor.
Proceedings of the International Conference on Parallel Processing, 1987

1983
A Simulator of Homogeneous Multiprocessor Systems.
Proceedings of the First European Simulation Congress ESC 83, 1983


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