Erik Chmelar

According to our database, Erik Chmelar authored at least 8 papers between 2003 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Inconsistent Fail due to Limited Tester Timing Accuracy.

Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Session Abstract.

Erik Chmelar, Edward J. McCluskey

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005

Segmented Addressable Scan Architecture.

Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

FPGA Bridging Fault Detection and Location via Differential I{DDQ}.

Erik Chmelar, Shahin Toutounchi

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Minimizing the number of test configurations for FPGAs.

Erik Chmelar

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Subframe multiplexing for FPGA manufacturing test configuration.

Erik Chmelar

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003

FPGA Interconnect Delay Fault Testing.

Erik Chmelar

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003