Erik Brockmeyer

According to our database1, Erik Brockmeyer authored at least 35 papers between 1998 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
Statistical Performance Analysis and Estimation for Parallel Multimedia Processing.
J. Signal Process. Syst., 2010

2009
Design and Tool Flow of Multimedia MPSoC Platforms.
J. Signal Process. Syst., 2009

Exploring parallelizations of applications for MPSoC platforms using MPA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An automatic scratch pad memory management tool and MPEG-4 encoder case study.
Proceedings of the 45th Design Automation Conference, 2008

2007
DRDU: A data reuse analysis technique for efficient scratch-pad memory management.
ACM Trans. Design Autom. Electr. Syst., 2007

Design-time application mapping and platform exploration for MP-SoC customised run-time management.
IET Comput. Digit. Tech., 2007

The Impact of Higher Communication Layers on NoC Supported MP-SoCs.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

2006
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Systematic Preprocessing of Data Dependent Constructs for Embedded Systems.
J. Low Power Electron., 2006

Pareto-Based Application Specification for MP-SoC Customized Run-Time Management.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Statistical Performance Analysis and Estimation of Coarse Grain Parallel Multimedia Processing System.
Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 2006

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.
Proceedings of the 43rd Design Automation Conference, 2006

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm.
J. VLSI Signal Process., 2005

Optimised Mapping of the QSDPCM Video Codec on MPARM: Shared Bus is not the Bottleneck.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Improving the Memory Bandwidth Utilization Using Loop Transformations.
Proceedings of the Integrated Circuit and System Design, 2005

Design-Time Application Exploration for MP-SoC Customized Run-Time Management.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
Proceedings of the 2005 Design, 2005

2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
Proceedings of the Computer Systems: Architectures, 2004

Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies.
Proceedings of the 2004 Design, 2004

2003
Estimating influence of data layout optimizations on SDRAM energy consumption.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations.
Proceedings of the 2003 Design, 2003

Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor.
Proceedings of the 2003 Design, 2003

2002
Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia Processor.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Memory addressing organization for stream-based reconfigurable computing.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Data Access and Storage Management for Embedded Programmable Processors.
Kluwer, ISBN: 978-0-7923-7689-7, 2002

2001
Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2001

Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Des. Test Comput., 2001

2000
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor.
IEEE Trans. Multim., 1999

Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Code Transformations for Reduced Data Transfer and Storage in Low Power Realisations of MPEG-4 Full-Pel Motion Estimation.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998


  Loading...