Éricles Sousa

According to our database, Éricles Sousa authored at least 17 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

*-Predictable MPSoC execution of real-time control applications using invasive computing.

Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich

Concurr. Comput. Pract. Exp., 2021

2018

Memory and interface architectures for invasive tightly coupled processor arrays = Speicher- und Schnittstellenarchitekturen für invasive eng gekoppelte Prozessorfelder.

Éricles Sousa

PhD thesis, 2018

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.

Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.

Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel

IEEE Trans. Computers, 2017

A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays.

Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays.

Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016

Dark silicon management: an integrated and coordinated cross-layer approach.

Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel

it Inf. Technol., 2016

2015

Resource-awareness on heterogeneous MPSoCs for image processing.

Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel

J. Syst. Archit., 2015

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.

Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays.

Éricles Sousa, Frank Hannig, Jürgen Teich

Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

2014

Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures.

Éricles Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Resource-aware Computer Vision Algorithms on Heterogeneous MPSoC Architectures.

Éricles Sousa

Proceedings of the 8th Joint Workshop of the German Research Training Groups in Computer Science, 2014

Self-adaptive harris corner detector on heterogeneous many-core processor.

Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms.

Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich

Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013

A prototype of an adaptive computer vision algorithm on MPSoC architecture.

Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays.

Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2011

An Analytical Model Proposed for Evaluating Efficiency of Partitioning Code in Hybrid Architectures Based on DSP and FPGA.

Éricles Rodrigues Sousa, Luis Meloni

Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011