Erich F. Haratsch

According to our database, Erich F. Haratsch authored at least 37 papers between 2000 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

Syndrome-Coupled Rate-Compatible Error-Correcting Codes: Theory and Application.

Pengfei Huang, Yi Liu, Xiaojie Zhang, Paul H. Siegel, Erich F. Haratsch

IEEE Trans. Inf. Theory, 2020

2018

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation.

Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu

Proc. ACM Meas. Anal. Comput. Syst., 2018

Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming.

Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch

CoRR, 2018

Read Disturb Errors in MLC NAND Flash Memory.

Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu

CoRR, 2018

Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory.

Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Saugata Ghose, Onur Mutlu

CoRR, 2018

HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness.

Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives.

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu

Proc. IEEE, 2017

Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery.

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu

CoRR, 2017

Syndrome-coupled rate-compatible error-correcting codes.

Pengfei Huang, Yi Liu, Xiaojie Zhang, Paul H. Siegel, Erich F. Haratsch

Proceedings of the 2017 IEEE Information Theory Workshop, 2017

Correcting errors by natural redundancy.

Anxiao Jiang, Pulakesh Upadhyaya, Erich F. Haratsch, Jehoshua Bruck

Proceedings of the 2017 Information Theory and Applications Workshop, 2017

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques.

Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016

Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory.

Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu

IEEE J. Sel. Areas Commun., 2016

Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs.

Meysam Asadi, Erich F. Haratsch, Aleksandar Kavcic, Narayana Prasad Santhanam

IEEE J. Sel. Areas Commun., 2016

2015

Write process modeling in MLC flash memories using renewal theory.

Meysam Asadi, Erich F. Haratsch, Aleksandar Kavcic, Narayana P. Santhanam

Proceedings of the IEEE International Symposium on Information Theory, 2015

A study of polar codes for MLC NAND flash memories.

Yue Li, Hakim Alhussien, Erich F. Haratsch, Anxiao Andrew Jiang

Proceedings of the International Conference on Computing, Networking and Communications, 2015

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery.

Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Joint decoding of content-replication codes for flash memories.

Qing Li, Huan Chang, Anxiao Jiang, Erich F. Haratsch

Proceedings of the 53rd Annual Allerton Conference on Communication, 2015

2014

Neighbor-cell assisted error correction for MLC NAND flash memories.

Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman S. Unsal, Adrián Cristal, Ken Mai

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Noise modeling and capacity analysis for NAND flash memories.

Qing Li, Anxiao Jiang, Erich F. Haratsch

Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014

2013

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation.

Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling.

Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime.

Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal, Osman S. Ünsal, Ken Mai

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis.

Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).

Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

FPGA-Based Solid-State Drive Prototyping Platform.

Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2007

Serial Sum-Product Architecture for Low-Density Parity-Check Codes.

Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei

Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders.

Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei

Proceedings of the Global Communications Conference, 2007

2006

High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor.

Hao Zhong, Tong Zhang, Erich F. Haratsch

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel.

Hao Zhong, Tong Zhang, Erich F. Haratsch

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Digital signal processing in read channels.

Erich F. Haratsch, Z. A. Keirn

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Trellis-based detection for high-speed data communications.

Erich F. Haratsch

PhD thesis, 2004

2002

Equalization and FEC techniques for optical transceivers.

Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Michael Shaffer, Leilei Song, Meng-Lin Yu

IEEE J. Solid State Circuits, 2002

2001

A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet.

Erich F. Haratsch, Kamran Azadet

IEEE J. Solid State Circuits, 2001

2000

High-speed reduced-state sequence estimation.

Erich F. Haratsch, Kamran Azadet

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback.

Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet

Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000

Pipelined reduced-state sequence estimation.

Erich F. Haratsch, Kamran Azadet

Proceedings of the Global Telecommunications Conference, 2000. GLOBECOM 2000, San Francisco, CA, USA, 27 November, 2000

A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet.

Erich F. Haratsch, Kamran Azadet

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000