Erica Tena
Orcid: 0000-0002-8905-5715
According to our database1,
Erica Tena
authored at least 27 papers
between 2012 and 2024.
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Bibliography
2024
Sensors, March, 2024
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
IEEE Embed. Syst. Lett., 2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors, 2021
IEEE Access, 2021
2020
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.
ACM J. Emerg. Technol. Comput. Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.
Int. J. Circuit Theory Appl., 2019
2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview.
Int. J. Circuit Theory Appl., 2017
2016
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.
Int. J. Circuit Theory Appl., 2016
Secure cryptographic hardware implementation issues for high-performance applications.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Industrial Technology, 2015
2014
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012