Eric Y. Chou

According to our database, Eric Y. Chou authored at least 5 papers between 1995 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture.

Eric Y. Chou, A. J. Budrys, Kit M. Cham

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1996

A neural network communication equalizer with optimized solution capability.

David C. Chen, Bing J. Sheu, Eric Y. Chou

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995

A hippocampal model implementation using VLSI table-look-up and model-based approaches.

Richard H. Tsai, Eric Y. Chou, Bing J. Sheu, Theodore W. Berger

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

A compact VLSI design for recursive neural networks with hardware annealing capability.

Eric Y. Chou, Bing J. Sheu, Steve H. Jen

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

VLSI design of densely-connected array processors.

Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995