Eric Tune

According to our database¹, Eric Tune authored at least 9 papers between 2001 and 2015.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2015

Large-scale cluster management at Google with Borg.

[BibT_eX]

[DOI]

Proceedings of the Tenth European Conference on Computer Systems, 2015

2013

Optimizing Google's warehouse scale computers: The NUMA experience.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

CPI<sup>2</sup>: CPU performance isolation for shared compute clusters.

[BibT_eX]

[DOI]

Proceedings of the Eighth Eurosys Conference 2013, 2013

2010

Google-Wide Profiling: A Continuous Profiling Infrastructure for Data Centers.

[BibT_eX]

[DOI]

IEEE Micro, 2010

2004

Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

2002

Loose Loops Sink Chips.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Quantifying Instruction Criticality.

[BibT_eX]

[DOI]

Eric Tune

Dean M. Tullsen

Brad Calder

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

Reducing power with dynamic critical path information.

[BibT_eX]

[DOI]

John S. Seng

Eric Tune

Dean M. Tullsen

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Dynamic Prediction of Critical Path Instructions.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Eric Tune

Timeline

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Links

On csauthors.net:

Bibliography

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