Eric Rotenberg

According to our database, Eric Rotenberg authored at least 63 papers between 1996 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Post-Fabrication Microarchitecture.

Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary, Shubham Bhawalkar, Rohit Singh, Eric Rotenberg

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

Post-Silicon Microarchitecture.

Chanchal Kumar, Aayush Chaudhary, Shubham Bhawalkar, Utkarsh Mathur, Saransh Jain, Adith Vastrad, Eric Rotenberg

IEEE Comput. Archit. Lett., 2020

Slipstream Processors Revisited: Exploiting Branch Sets.

Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Eric Rotenberg

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2017

A case for standard-cell based RAMs in highly-ported superscalar processor structures.

Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.

Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores.

Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Fast register consolidation and migration for heterogeneous multi-core processors.

Elliott Forbes, Eric Rotenberg

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

AnyCore-1: A comprehensively adaptive 4-way superscalar processor.

Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Physical design of a 3D-stacked heterogeneous multi-core processor.

Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching.

Rami Sheikh, James Tuck, Eric Rotenberg

IEEE Trans. Computers, 2015

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor.

Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Computing in 3D.

Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Computing in 3D.

Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores.

Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Co-simulation framework for streamlining microprocessor development on standard ASIC design flow.

Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

3D-enabled customizable embedded computer (3DECC).

Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

Hetero² 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors.

Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon

Proceedings of the International Symposium on Quality Electronic Design, 2013

Rationale for a 3D heterogeneous multi-core processor.

Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors.

Sandeep Navada, Niket K. Choudhary, Salil V. Wadhavkar, Eric Rotenberg

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

Design of controller for L2 cache mapped in Tezzaron stacked DRAM.

Nyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

FabScalar: Automating Superscalar Core Design.

Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg

IEEE Micro, 2012

A physical design study of fabscalar-generated superscalar cores.

Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Control-Flow Decoupling.

Rami Sheikh, James Tuck, Eric Rotenberg

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

FPGA modeling of diverse superscalar processors.

Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

2011

FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template.

Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

EXACT: explicit dynamic-branch prediction with active updates.

Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg

Proceedings of the 7th Conference on Computing Frontiers, 2010

Criticality-driven superscalar design space exploration.

Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

The importance of accurate task arrival characterization in the design of processing cores.

Hashem Hashemi Najaf-abadi, Eric Rotenberg

Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Architectural Contesting.

Hashem Hashemi Najaf-abadi, Eric Rotenberg

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Core-Selectability in Chip Multiprocessors.

Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg

Proceedings of the PACT 2009, 2009

2008

Configurational Workload Characterization.

Hashem Hashemi Najaf-abadi, Eric Rotenberg

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Coverage of a microarchitecture-level fault check regimen in a superscalar processor.

Vimal K. Reddy, Eric Rotenberg

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2007

ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling.

Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg

IEEE Trans. Computers, 2007

Architectural <i>contesting</i>: exposing and exploiting temperamental behavior.

Hashem Hashemi Najaf-abadi, Eric Rotenberg

SIGARCH Comput. Archit. News, 2007

Transparent control independence (TCI).

Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance.

Vimal K. Reddy, Eric Rotenberg

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2006

FAST: Frequency-aware static timing analysis.

Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg

ACM Trans. Embed. Comput. Syst., 2006

Non-uniform program analysis & repeatable execution constraints: exploiting out-of-order processors in real-time systems.

Aravindh Anantaraman, Eric Rotenberg

SIGBED Rev., 2006

The State of ZettaRAM.

Eric Rotenberg, Ravi V. Venkatesan

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Assertion-Based Microarchitecture Design for Improved Reliability.

Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM.

Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.

Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005

Tapping ZettaRAM^TM for Low-Power Memory Systems.

Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing.

Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg

Proceedings of the 2005 International Conference on Compilers, 2005

2004

A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors.

Jinson Koppanalil, Eric Rotenberg

IEEE Trans. Computers, 2004

Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA).

Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller

Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

Safely exploiting multithreaded processors to tolerate memory latency in real-time systems.

Ali El-Haj-Mahmoud, Eric Rotenberg

Proceedings of the 2004 International Conference on Compilers, 2004

2003

Adaptive mode control: A static-power-efficient cache design.

Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte

ACM Trans. Embed. Comput. Syst., 2003

Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems.

Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Slipstream Execution Mode for CMP-Based Multiprocessors.

Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

A Large, Fast Instruction Window for Tolerating Cache Misses.

Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

A case for dynamic pipeline scaling.

Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg

Proceedings of the International Conference on Compilers, 2002

2001

Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems.

Eric Rotenberg

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000

Control Independence in Trace Processors.

Eric Rotenberg, James E. Smith

J. Instr. Level Parallelism, 2000

A study of slipstream processors.

Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Slipstream Processors: Improving both Performance and Fault Tolerance.

Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg

Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999

A Trace Cache Microarchitecture and Evaluation.

Eric Rotenberg, Steve Bennett, James E. Smith

IEEE Trans. Computers, 1999

A Study of Control Independence in Superscalar Processors.

Eric Rotenberg, Quinn Jacobson, James E. Smith

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.

Eric Rotenberg

Proceedings of the Digest of Papers: FTCS-29, 1999

1997

Trace Processors.

Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Path-Based Next Trace Prediction.

Quinn Jacobson, Eric Rotenberg, James E. Smith

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

1996

Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.

Eric Rotenberg, Steve Bennett, James E. Smith

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Assigning Confidence to Conditional Branch Predictions.

Erik Jacobsen, Eric Rotenberg, James E. Smith

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996