Eric Rentschler

According to our database, Eric Rentschler authored at least 4 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Techniques for Debug of Low Power SoCs.

Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra

Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

2016

Special panel session IIB: "System validation and silicon debug - Is standardization possible?".

Mike Ricchetti, Eric Rentschler, Amit Majumdar, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015

Quick error detection tests with fast runtimes for effective post-silicon validation and debug.

David Lin, Eswaran S, Sharad Kumar, Eric Rentschler, Subhasish Mitra

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013

Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs.

Arie Margulis, David Akselrod, Eric Rentschler, Mike Ricchetti

IEEE Des. Test, 2013