Eric Müller
Orcid: 0000-0001-5880-2012Affiliations:
- Heidelberg University, Germany (PhD 2014)
According to our database1,
Eric Müller
authored at least 36 papers
between 2009 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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Bibliography
2024
Proceedings of the Neuro Inspired Computational Elements Conference, 2024
2023
Simulation-based inference for model parameterization on analog neuromorphic hardware.
Neuromorph. Comput. Eng., December, 2023
Simulation-based Inference for Model Parameterization on Analog Neuromorphic Hardware [data].
Dataset, November, 2023
From clean room to machine room: commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system.
Neuromorph. Comput. Eng., September, 2023
Simulation-based Inference for Model Parameterization on Analog Neuromorphic Hardware [data].
Dataset, September, 2023
Dataset, April, 2023
hxtorch.snn: Machine-learning-inspired Spiking Neural Network Modeling on BrainScaleS-2.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023
2022
IEEE Open J. Circuits Syst., 2022
Proceedings of the NICE 2022: Neuro-Inspired Computational Elements Conference, 2022
2021
2020
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020
Live Demonstration: Versatile Emulation of Spiking Neural Networks on an Accelerated Neuromorphic Substrate.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Versatile Emulation of Spiking Neural Networks on an Accelerated Neuromorphic Substrate.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Brain-Inspired Hardware for Artificial Intelligence: Accelerated Learning in a Physical-Model Spiking Neural Network.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019
2018
Frontiers Neuroinformatics, 2018
2017
Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.
CoRR, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
2014
2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biol. Cybern., 2011
2010
Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Live demonstration: Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System.
Proceedings of the Artificial Neural Networks and Intelligent Information Processing, 2010
2009
Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.
Frontiers Neuroinformatics, 2009