Eric Liau

According to our database1, Eric Liau authored at least 8 papers between 2003 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Links

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Bibliography

2008
Efficient High-Speed Interface Verification and Fault Analysis.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
Fully automated semiconductor operating condition testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Computational intelligence based testing for semiconductor measurement systems.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Computational Intelligence Characterization Method of Semiconductor Device.
Proceedings of the 2005 Design, 2005

2003
Evolution of automatic semiconductor test equipment: automatic test pattern learning, classification, optimisation and generation for power supply noise.
Proceedings of the IEEE International Conference on Virtual Environments, 2003

Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits.
Proceedings of the 8th European Test Workshop, 2003


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