Eric Jia-Wei Fang

Orcid: 0009-0008-6190-5264

Affiliations:
  • MediaTek Inc., Hsinchu, Taiwan


According to our database1, Eric Jia-Wei Fang authored at least 25 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Vmin Prediction Using Nondestructive Stress Test.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Will Dynamic Foveation Boost Cloud VR Gaming Experience?
Proceedings of the 33rd Workshop on Network and Operating System Support for Digital Audio and Video, 2023

Modeling Gamer Quality-of-Experience Using a Real Cloud VR Gaming Testbed.
Proceedings of the 15th International Workshop on Immersive Mixed and Virtual Environment Systems, 2023

A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
Enhancing situational awareness with adaptive firefighting drones: leveraging diverse media types and classifiers.
Proceedings of the MMSys '22: 13th ACM Multimedia Systems Conference, Athlone, Ireland, June 14, 2022

Optimal Camera Placement for 6 Degree-of-Freedom Immersive Video Streaming Without Accessing 3D Scenes.
Proceedings of the IXR@MM 2022: Proceedings of the 1st Workshop on Interactive eXtended Reality, 2022

ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption.
Proceedings of the IEEE International Test Conference, 2022

2021
Chip Performance Prediction Using Machine Learning Techniques.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning.
Proceedings of the IEEE International Test Conference, 2021

35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Automatic IR-Drop ECO Using Machine Learning.
Proceedings of the IEEE International Test Conference in Asia, 2020

2018
IR drop prediction of ECO-revised circuits using machine learning.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Machine-learning-based dynamic IR drop prediction for ECO.
Proceedings of the International Conference on Computer-Aided Design, 2018

2015
IR to routing challenge and solution for interposer-based design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2010
ECO Timing Optimization Using Spare Cells and Technology Remapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Flip-chip routing with unified area-I/O pad assignments for package-board co-design.
Proceedings of the 46th Design Automation Conference, 2009

2008
Routing for chip-package-board co-design considering differential pairs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Area-I/O flip-chip routing for chip-package co-design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

ECO timing optimization using spare cells.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.
Proceedings of the 44th Design Automation Conference, 2007

2005
A routing algorithm for flip-chip design.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005


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