Eric Beyne

According to our database, Eric Beyne authored at least 90 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias.

P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology.

S.-H. Lin, Marko Simicic, N. Pantano, S.-H. Chen, Geert Van der Plas, Eric Beyne, Piet Wambacq

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Clean Dicing: An Alternative Blade Dicing Technique for Minimising Particles in 3D Heterogeneous Integration.

Akito Hiro, Damien Jon Leech, Geert Schoofs, John Slabbekoorn, Alain Phommahaxay, Koen Kennes, Gerald Beyer, Eric Beyne

Proceedings of the International 3D Systems Integration Conference, 2024

2023

Impact of gate-level clustering on automated system partitioning of 3D-ICs.

Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic

Microelectron. J., September, 2023

IP Session on Chiplet: Design, Assembly, and Test.

Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN).

Eric Beyne, Anne Jourdain, Gerald Beyer

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips.

Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs.

Mohamed Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic

Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor.

Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne

IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Backside Power Delivery for High-Performance Computing Systems.

Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne

IEEE Trans. Very Large Scale Integr. Syst., 2022

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.

Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

(Why do we need) Wireless Heterogeneous Integration (anyway?).

Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, Nelson Pinho, Tomas Webers, Dimitrios Velenis, Andy Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.

Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism.

Lin Hou, Emmanuel Chery, Kristof Croes, Davide Tierno, Soon Aik Chew, Yangyin Chen, Peter Rakbin, Eric Beyne

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021

Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy.

Kristof J. P. Jacobs, Michele Stucchi, Eric Beyne

IEEE Trans. Instrum. Meas., 2021

Design and Technology Solutions for 3D Integrated High Performance Systems.

Geert Van der Plas, Eric Beyne

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).

Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

2019

Process Complexity and Cost Considerations of Multi-Layer Die Stacks.

Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.

Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Protective Layer for Collective Die to Wafer Hybrid Bonding.

Fumihiro Inoue, Julien Bertheau, Samuel Suhard, Alain Phommahaxay, Takuya Ohashi, Tetsuro Kinoshita, Yohei Kinoshita, Eric Beyne

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly.

Melina Lofrano, Vladimir Cherman, Mario Gonzalez, Eric Beyne

Microelectron. Reliab., 2018

A study on substrate noise coupling among TSVs in 3D chip stack.

Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne

IEICE Electron. Express, 2018

TSV process-induced MOS reliability degradation.

Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne, Kristof Croes

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Stress mitigation of 3D-stacking/packaging induced stresses.

Kristof Croes, Vladimir Cherman, Melina Lofrano, Houman Zahedmanesh, Luka Kljucar, Mario Gonzalez, Ingrid De Wolf, Zsolt Tökei, Eric Beyne

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.

Luka Kljucar, Mario Gonzalez, Kristof Croes, Ingrid De Wolf, Joke De Messemaeker, Gayle Murdoch, Philip Nolmans, Joeri De Vos, Jürgen Bömmels, Eric Beyne, Zsolt Tökei

Microelectron. Reliab., 2017

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices.

Kristof J. P. Jacobs, T. Wang, Michele Stucchi, Mario Gonzalez, Kris Croes, Ingrid De Wolf, Eric Beyne

Microelectron. Reliab., 2017

2016

Reliability Challenges Related to TSV Integration and 3-D Stacking.

Kristof Croes, Joke De Messemaeker, Yunlong Li, Wei Guo, Olalla Varela Pedreira, Vladimir Cherman, Michele Stucchi, Ingrid De Wolf, Eric Beyne

IEEE Des. Test, 2016

The 3-D Interconnect Technology Landscape.

Eric Beyne

IEEE Des. Test, 2016

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects.

Joeri De Vos, Lan Peng, Alain Phommahaxay, Joost Van Ongeval, Andy Miller, Eric Beyne, Florian Kurz, Thomas Wagenleiter, Markus Wimplinger, Thomas Uhrmann

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.

C. Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Extreme wafer thinning optimization for via-last applications.

Anne Jourdain, Joeri De Vos, Fumihiro Inoue, Kenneth J. Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Edward Walsby, Jash Patel, Oliver Ansell, Janet Hopkins, Huma Ashraf, Dave Thomas

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module.

Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne, Mohand Brouri, Praveen Nalla, Sanjay Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Die to wafer 3D stacking for below 10um pitch microbumps.

Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bex, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June Rebibis, Andy Miller

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling.

Nabi Nabiollahi, Nele Moelans, Mario Gonzalez, Joke De Messemaeker, Christopher J. Wilson, Kristof Croes, Eric Beyne, Ingrid De Wolf

Microelectron. Reliab., 2015

Active-lite interposer for 2.5 & 3D integration.

Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean

Proceedings of the Symposium on VLSI Circuits, 2015

Impact of oxide liner properties on TSV Cu pumping and TSV stress.

Joke De Messemaeker, O. Varela Pedreira, A. Moussa, Nabi Nabiollahi, Kris Vanstreels, Stefaan Van Huylenbroeck, Harold Philipsen, Patrick Verdonck, Bart Vandevelde, Ingrid De Wolf, Eric Beyne, Kris Croes

Proceedings of the IEEE International Reliability Physics Symposium, 2015

Thermal experimental and modeling analysis of high power 3D packages.

Herman Oprins, Vladimir Cherman, Geert Van der Plas, F. L. T. Maggioni, Joeri De Vos, Eric Beyne

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Through silicon via to FinFET noise coupling in 3-D integrated circuits.

A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Processing active devices on Si interposer and impact on cost.

Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics.

Soon-Wook Kim, Lan Peng, Andy Miller, Gerald Beyer, Eric Beyne, Chung-Sun Lee

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

3D system integration research at IMEC.

Eric Beyne

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling.

Bart Vandevelde, Andrej Ivankovic, B. Debecker, Melina Lofrano, Kris Vanstreels, Wei Guo, Vladimir Cherman, Marcel Gonzalez, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Zsolt Tokei

Microelectron. Reliab., 2014

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias.

Yunlong Li, Stefaan Van Huylenbroeck, Els Van Besien, Xiaoping Shi, Chen Wu, Michele Stucchi, Gerald Beyer, Eric Beyne, Ingrid De Wolf, Kristof Croes

Microelectron. Reliab., 2014

Fast convolution based thermal model for 3D-ICs: Methodology, accuracy analysis and package impact.

F. L. T. Maggioni, Herman Oprins, Eric Beyne, Ingrid De Wolf, Martine Baelmans

Microelectron. J., 2014

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.

Prashant Agrawal, Dragomir Milojevic, Praveen Raghavan, Francky Catthoor, Liesbet Van der Perre, Eric Beyne, Ravi Varadarajan

IEEE Embed. Syst. Lett., 2014

Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges.

Joeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Analysis of 3D interconnect performance: Effect of the Si substrate resistivity.

X. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

Design issues in heterogeneous 3D/2.5D integration.

Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Si interposer build-up options and impact on 3D system cost.

Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.

Wei Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, Mario Gonzalez, Yann Civale, Augusto Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, Kenneth J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne, Bart Swinnen

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

Cu pumping in TSVs: Effect of pre-CMP thermal budget.

Ingrid De Wolf, Kris Croes, O. Varela Pedreira, Riet Labie, Augusto Redolfi, M. Van De Peer, Kris Vanstreels, C. Okoro, Bart Vandevelde, Eric Beyne

Microelectron. Reliab., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.

Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal

IEEE J. Solid State Circuits, 2011

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.

Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas

Proceedings of the Design, Automation and Test in Europe, 2011

3D heterogeneous system integration: application driver for 3D technology development.

Eric Beyne, Pol Marchal, Geert Van der Plas

Proceedings of the 48th Design Automation Conference, 2011

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.

Alain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

3D stacking using ultra thin dies.

Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, Wenqi Zhang, Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Analysis of microbump induced stress effects in 3D stacked IC technologies.

Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, Wenqi Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

3D stacking using Cu-Cu direct bonding.

Y. H. Hu, C. S. Liu, M. J. Lii, Kenneth J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

In-line metrology and inspection for process control during 3D stacking of IC's.

Sandip Halder, Ingrid De Wolf, Alain Phommahaxay, Andy Miller, Mireille Maenhoudt, Gerald Beyer, Bart Swinnen, Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions.

Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

In-tier diagnosis of power domains in 3D TSV ICs.

Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Design issues and considerations for low-cost 3D TSV IC technology.

Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.

Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Cost effectiveness of 3D integration options.

Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2010

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications.

Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen

Proceedings of the IEEE International Conference on 3D System Integration, 2010

A novel concept for ultra-low capacitance via-last TSV.

Yann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.

Paul Marchal, Bruno Bougard, Guruprasad Katti, Michele Stucchi, Wim Dehaene, Antonis Papanikolaou, Diederik Verkest, Bart Swinnen, Eric Beyne

Proc. IEEE, 2009

Impact of 3D design choices on manufacturing cost.

Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2009

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).

Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping.

Yann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen, P. Jaenen, Rahul Agarwal, F. Duval, Philippe Soussan, Youssef Travaly, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007

Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages.

Bart Vandevelde, Mario Gonzalez, Paresh Limaye, Petar Ratchev, Eric Beyne

Microelectron. Reliab., 2007

Tutorial T7A: Advanced IC Packaging.

Eric Beyne

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Wafer-level package interconnect options.

J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne

IEEE Trans. Very Large Scale Integr. Syst., 2006

Technologies for highly miniaturized autonomous sensor networks.

Kris Baert, Bert Gyselinckx, Tom Torfs, Vladimir Leonov, Refet Firat Yazicioglu, Steven Brebels, Stéphane Donnay, J. Vanfletern, M. Pastreen, Eric Beyne, Chris Van Hoof

Microelectron. J., 2006

Constant impedance scaling paradigm for interconnect synthesis.

J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Efficient Link Architecture for On-Chip Serial links and Networks.

J. Balachandran, Maarten Kuijk, Steven Brebels, Geert Carchon, Walter De Raedt, Bart Nauwelaers, Eric Beyne

Proceedings of the International Symposium on System-on-Chip, 2006

Constant Impedance Scaling Paradigm for Scaling LC transmission lines.

J. Balachandran, Steven Brebels, Geert Carchon, Walter De Raedt, Eric Beyne, Maarten Kuijk, Bart Nauwelaers

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier.

Mathieu Vanden Bulcke, Kris Baert, Eric Beyne, Mario Gonzalez, Christophe Winters, Tomas Webers

Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006

Analysis and modeling of power grid transmission lines.

J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Package level interconnect options.

J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne

Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

2004

Characterization and FE analysis on the shear test of electronic materials.

Marcel Gonzalez, Bart Vandevelde, R. Van Hoof, Eric Beyne

Microelectron. Reliab., 2004

2003

Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages.

Bart Vandevelde, Dominiek Degryse, Eric Beyne, Eric Roose, Dorina Corlatan, Guido Swaelen, Geert Willems, Filip Christiaens, Alcatel Bell, Dirk Vandepitte

Microelectron. Reliab., 2003

Advantage of In-situ over Ex-situ techniques as reliability tool: Aging kinetics of Imec's MCM-D discrete passives devices.

Philippe Soussan, G. Lekens, R. Dreesen, Ward De Ceuninck, Eric Beyne

Microelectron. Reliab., 2003

Direct gold and copper wires bonding on copper.

Hong Meng Ho, Wai Lam, Serguei Stoukatch, Petar Ratchev, Charles J. Vath, Eric Beyne

Microelectron. Reliab., 2003

The influence of packaging materials on RF performance.

Arun Chandrasekhar, Steven Brebels, Serguei Stoukatch, Eric Beyne, Walter De Raedt, Bart Nauwelaers

Microelectron. Reliab., 2003

2000

Chip-package codesign of a low-power 5-GHz RF front end.

Stéphane Donnay, Philip Pieters, Kristof Vaesen, Wim Diels, Piet Wambacq, Walter De Raedt, Eric Beyne, Marc Engels, Ivo Bolsens

Proc. IEEE, 2000

1996

Design of Test Modules for the Analysis of MCM Interconnects.

Claudio Truzzi, Eric Beyne, Edwin Ringoot

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Signal propagation in high-speed MCM circuits.

Claudio Truzzi, Eric Beyne, Edwin Ringoot, J. Peeters

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995