Erfan Azarkhish

According to our database, Erfan Azarkhish authored at least 14 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.

Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini

ACM Trans. Embed. Comput. Syst., September, 2022

2021

A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge.

Petar Jokic, Erfan Azarkhish, Régis Cattenoz, Engin Türetken, Luca Benini, Stéphane Emery

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Single-Battery Cooperative Sensors For Multi-Lead Long Term Ambulatory ECG Measurement.

Komail M. H. Badami, Marc Pons Solé, Erfan Azarkhish, André Fivaz, Michaël Rapin, Olivier Chételat, Stéphane Emery

Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2019

A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control.

Marc Pons Solé, Andre Bischof, Lorenzo Bergamini, Philippe Dallemagne, Stéphane Emery, Komail M. H. Badami, Jiang Deng, Themistoklis Mavrogordatos, Erfan Azarkhish, Loïc Zahnd, Costantino Cosentino, Marcin K. Augustyniak, Yingyun Zha

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.

Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini

IEEE Trans. Parallel Distributed Syst., 2018

2017

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.

Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters.

Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini

IEEE Embed. Syst. Lett., 2017

2016

Memory Hierarchy Design for Next Generation Scalable Many-core Platforms.

Erfan Azarkhish

PhD thesis, 2016

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.

Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015

A Modular Shared L2 Memory Design for 3-D Integration.

Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., 2015

High performance AXI-4.0 based interconnect for extensible smart memory cubes.

Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013

A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects.

Erfan Azarkhish, Igor Loi, Luca Benini

IET Comput. Digit. Tech., 2013

3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.

Erfan Azarkhish, Igor Loi, Luca Benini

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A high-performance multiported L2 memory IP for scalable three-dimensional integration.

Erfan Azarkhish, Igor Loi, Luca Benini

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013