Enrique Prefasi

Orcid: 0000-0003-0338-9624

Affiliations:
  • Carlos III University, Madrid, Spain


According to our database1, Enrique Prefasi authored at least 35 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024
An LC-tank based DCO for low-power high-speed applications using full-custom nMOS-type varactors.
Microelectron. J., 2024

2023
ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
A Novel Design Methodology for Low-Power, Low-Noise LC-Based Digital-Controlled Oscillators.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Multi-Gigabit Transceivers for Optical Data Communications From the Standardization Perspective.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Towards the Multi-Gigabit Ethernet for the Automotive Industry.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Fully-Differential Switched-Capacitor Dual-Slope Capacitance-To-Digital Converter (CDC) for a Capacitive Pressure Sensor.
Sensors, 2019

A 1-1 MASH using two Noise-Shaping Switched-Capacitor Dual-Slope converters.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018
VCO-ADC Resolution Enhancement Using Maximum Length Sequences.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Novel Multi-Bit Sigma-Delta Modulator using an Integrating SAR Noise-Shaped Quantizer.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Low-Power Auto-Zero Switched-Capacitor Dual-Slope Noise-Shaping Direct CDC.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications.
Sensors, 2017

A low-IF bandpass ΣΔ ADC for fully-integrated CMOS magnetic resonance imaging receivers.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensors.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2014
A 0.03mm<sup>2</sup>, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A distortion corrected passive RC noise shaping ADC for biomedical applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Analysis of VCO based noise shaping ADCs linearized by PWM modulation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm <sup>2</sup> 65 nm CMOS Circuit.
IEEE J. Solid State Circuits, 2011

1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A time encoded decimation filter for noise shaped power DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 0.1 mm<sup>2</sup>, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2009

Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Analog-to-Digital Conversion Using Noise Shaping and Time Encoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A subsampling bandpass SigmaDelta modulator with lumped and distributed resonators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A one-path quadrature bandpass ΣΔ modulator based on distributed resonators at 25 MHz IF.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

An A/D converter based on pulse width modulation and the walsh-hadamard transform.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2006
A continuous-time band-pass Sigma Delta modulator implemented in 0.35µm BiCMOS using transmission lines.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design of Cascaded Continuous-Time Sigma-Delta Modulators.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Analog to digital conversion using a Pulse Width Modulator and an irregular sampling decoder.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Synthesis of sigma delta modulators employing continuous time delays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A jitter insensitive continuous-time ΣΔ modulator using transmission lines.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004


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