Enrico Macii

Sukhan Lee

Birgit Vogel-Heuser

Proc. IEEE, 2021

Enhancing manufacturing intelligence through an unsupervised data-driven methodology for cyclic industrial processes.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2021

A compound of feature selection techniques to improve solar radiation forecasting.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2021

Solar radiation forecasting based on convolutional neural network and ensemble learning.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2021

Adaptive Test-Time Augmentation for Low-Power CPU.

[BibT_eX]

[DOI]

Luca Mocerino

CoRR, 2021

A Win-Win Algorithm for Learning the Flexibility of Aggregated Residential Appliances.

[BibT_eX]

[DOI]

IEEE Access, 2021

Comparative Analysis of Neural Networks Techniques to Forecast Global Horizontal Irradiance.

[BibT_eX]

[DOI]

IEEE Access, 2021

On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets.

[BibT_eX]

[DOI]

Luca Mocerino

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets.

[BibT_eX]

[DOI]

Luca Mocerino

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Configuring an Embedded Neuromorphic Coprocessor Using a RISC-V Chip for Enabling Edge Computing Applications.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

ACME: An Energy-Efficient Approximate Bus Encoding for I2C.

[BibT_eX]

[DOI]

Chen Xie

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference.

[BibT_eX]

[DOI]

Alberto Dequino

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Robust and Energy-Efficient PPG-Based Heart-Rate Monitoring.

[BibT_eX]

[DOI]

Matteo Risso

Antonio Giuseppe Varrella

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Bayesian approach to Expert Gate Incremental Learning.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2021

Image analytics and machine learning for in-situ defects detection in Additive Manufacturing.

[BibT_eX]

[DOI]

Davide Cannizzaro

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks.

[BibT_eX]

[DOI]

Matteo Risso

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Design of District-level Photovoltaic Installations for Optimal Power Production and Economic Benefit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 45th Annual Computers, Software, and Applications Conference, 2021

Forecasting the Grid Power Demand of Charging Stations from EV Drivers' Attitude.

[BibT_eX]

[DOI]

Alberto Bocca

Proceedings of the IEEE 45th Annual Computers, Software, and Applications Conference, 2021

Ultra-compact binary neural networks for human activity recognition on RISC-V processors.

[BibT_eX]

[DOI]

Francesco Daghero

Chen Xie

Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020

Modeling and Simulation of Cyber-Physical Electrical Energy Systems With SystemC-AMS.

[BibT_eX]

[DOI]

Paolo Montuschi

IEEE Trans. Sustain. Comput., 2020

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Optimization Tools for ConvNets on the Edge.

[BibT_eX]

[DOI]

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

An Engineering Process model for managing a digitalised life-cycle of products in the Industry 4.0.

[BibT_eX]

[DOI]

Proceedings of the NOMS 2020, 2020

Exploiting "Uncertain" Deep Networks for Data Cleaning in Digital Pathology.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Biomedical Imaging, 2020

Data Driven Patient-Specialized Neural Networks for Blood Glucose Prediction.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Multimedia & Expo Workshops, 2020

A Spatial Correlation Analysis of Seismic and Flooding Events: Application to Italy.

[BibT_eX]

[DOI]

Alberto Bocca

Proceedings of the ICGDA 2020: 3rd International Conference on Geoinformatics and Data Analysis, 2020

Energy-Efficient Adaptive Machine Learning on IoT End-Nodes With Class-Dependent Confidence.

[BibT_eX]

[DOI]

Francesco Daghero

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Predicting Hard Disk Failures in Data Centers Using Temporal Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2020: Parallel Processing Workshops, 2020

A Diode-Aware Model of PV Modules from Datasheet Specifications.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Input-Dependent Edge-Cloud Mapping of Recurrent Neural Networks Inference.

[BibT_eX]

[DOI]

Daniele Salvatore Schiera

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Optimal Configuration and Placement of PV Systems in Building Roofs with Cost Analysis.

[BibT_eX]

[DOI]

Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

GAMES: A General-Purpose Architectural Model for Multi-energy System Engineering Applications.

[BibT_eX]

[DOI]

Luca Barbierato

Enrico Pons

Ettore Francesco Bompard

Andrea Lanzini

Romano Borchiellini

Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

2019

Battery-Aware Operation Range Estimation for Terrestrial and Aerial Electric Vehicles.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2019

A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors.

[BibT_eX]

[DOI]

Nicola Bombieri

Franco Fummi

ACM Trans. Design Autom. Electr. Syst., 2019

SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Automated Synthesis of Energy-Efficient Reconfigurable-Precision Circuits.

[BibT_eX]

[DOI]

IEEE Access, 2019

A SystemC-AMS Framework for the Design and Simulation of Energy Management in Electric Vehicles.

[BibT_eX]

[DOI]

IEEE Access, 2019

A Multi-Patient Data-Driven Approach to Blood Glucose Prediction.

[BibT_eX]

[DOI]

IEEE Access, 2019

CNN-Based Camera-less User Attention Detection for Smartphone Power Management.

[BibT_eX]

[DOI]

Matteo Ansaldi

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Battery-Aware Electric Truck Delivery Route Planner.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Optimal Input-Dependent Edge-Cloud Partitioning for RNN Inference.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Semi-Empirical Model of PV Modules Including Manufacturing I-V Mismatch.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Dynamic Beam Width Tuning for Energy-Efficient Recurrent Neural Networks.

[BibT_eX]

[DOI]

Francesco Panini

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Cloud-to-edge Architecture for Predictive Analytics.

[BibT_eX]

[DOI]

Proceedings of the Workshops of the EDBT/ICDT 2019 Joint Conference, 2019

Irradiance-Driven Partial Reconfiguration of PV Panels.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Low-Overhead Power Trace Obfuscation for Smart Meter Privacy.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Code Mapping in Heterogeneous Platforms Using Deep Learning and LLVM-IR.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Fog Computing Approach for Predictive Maintenance.

[BibT_eX]

[DOI]

Proceedings of the Advanced Information Systems Engineering Workshops, 2019

A New Unsupervised Predictive-Model Self-Assessment Approach That SCALEs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Congress on Big Data, 2019

PREMISES, a Scalable Data-Driven Service to Predict Alarms in Slowly-Degrading Multi-Cycle Industrial Processes.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Congress on Big Data, 2019

2018

Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy.

[BibT_eX]

[DOI]

Donghwa Shin

IEEE Trans. Very Large Scale Integr. Syst., 2018

LAPSE: Low-Overhead Adaptive Power Saving and Contrast Enhancement for OLEDs.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2018

Optimizing Network Traffic for Spiking Neural Network Simulations on Densely Interconnected Many-Core Neuromorphic Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

GIS-Based Software Infrastructure to Model PV Generation in Fine-Grained Spatio-Temporal Domain.

[BibT_eX]

[DOI]

IEEE Syst. J., 2018

Empirical derivation of upper and lower bounds of NBTI aging for embedded cores.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Composable Battery Model Templates Based on Manufacturers' Data.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

Aging and Cost Optimal Residential Charging for Plug-In EVs.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

Directed Graph Placement for SNN Simulation into a multi-core GALS Architecture.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Distributed Infrastructure for Multi-Energy-Systems Modelling and Co-simulation in Urban Districts.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Smart Cities and Green ICT Systems, 2018

Non-linear Autoregressive Neural Networks to Forecast Short-Term Solar Radiation for Photovoltaic Energy Predictions.

[BibT_eX]

[DOI]

Alessandro Aliberti

Giansalvo Cirrincione

Proceedings of the Smart Cities, Green Technologies and Intelligent Transport Systems, 2018

Forecasting Short-term Solar Radiation for Photovoltaic Energy Predictions.

[BibT_eX]

[DOI]

Alessandro Aliberti

Giansalvo Cirrincione

Proceedings of the 7th International Conference on Smart Cities and Green ICT Systems, 2018

iSTEP, an Integrated Self-Tuning Engine for Predictive Maintenance in Industry 4.0.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

Dynamic Bit-width Reconfiguration for Energy-Efficient Deep Learning Hardware.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Battery-Aware Energy Model of Drone Delivery Tasks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Optimal Topology-Aware PV Panel Floorplanning with Hybrid Orientation.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Battery-aware Design Exploration of Scheduling Policies for Multi-sensor Devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

IoT Software Infrastructure for Remote Monitoring of Patients with Chronic Metabolic Disorders.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Future Internet of Things and Cloud, 2018

GIS-based optimal photovoltaic panel floorplanning for residential installations.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

All-digital embedded meters for on-line power estimation.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Predicting the Oncogenic Potential of Gene Fusions Using Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence Methods for Bioinformatics and Biostatistics, 2018

Multiple alignment of packet sequences for efficient communication in a many-core neuromorphic system: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2018

Impact of graph partitioning on SNN placement for a multi-core neuromorphic architecture: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2018

Going Deeper into Colorectal Cancer Histopathology.

[BibT_eX]

[DOI]

Proceedings of the Biomedical Engineering Systems and Technologies, 2018

Colorectal Cancer Classification using Deep Convolutional Networks - An Experimental Study.

[BibT_eX]

[DOI]

Proceedings of the 11th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2018), 2018

2017

Approximate Energy-Efficient Encoding for Serial Interfaces.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

A Flexible Distributed Infrastructure for Real-Time Cosimulations in Smart Grids.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2017

A Software Toolchain for Variability Awareness on Heterogenous Multicore Platforms.

[BibT_eX]

[DOI]

Ramakrishna Nittala

IEEE Trans. Emerg. Top. Comput., 2017

A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Information Modeling for Virtual and Augmented Reality.

[BibT_eX]

[DOI]

IT Prof., 2017

A scalable middleware-based infrastructure for energy management and visualization in city districts.

[BibT_eX]

[DOI]

Francesco Gavino Brundu

EAI Endorsed Trans. Cloud Syst., 2017

Optimal content-dependent dynamic brightness scaling for OLED displays.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A Convolutional Neural Network Fully Implemented on FPGA for Embedded Platforms.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

An Efficient MPI Implementation for Multi-Coreneuromorphic Platforms.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

Workload-driven frequency-aware battery sizing.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

PVInGrid: A Distributed Infrastructure for Evaluating the Integration of Photovoltaic Systems in Smart Grid.

[BibT_eX]

[DOI]

Proceedings of the Technological Innovation for Smart Systems, 2017

A methodology for the design of dynamic accuracy operators by runtime back bias.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A circuit-equivalent battery model accounting for the dependency on load frequency.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Building Energy Modelling and Monitoring by Integration of IoT Devices and Building Information Models.

[BibT_eX]

[DOI]

Alessandro Aliberti

Francesca Maria Ugliotti

Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

A Multi-modal Brain Image Registration Framework for US-guided Neuronavigation Systems - Integrating MR and US for Minimally Invasive Neuroimaging.

[BibT_eX]

[DOI]

Proceedings of the 10th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2017), 2017

2016

Distributed Software Infrastructure for General Purpose Services in Smart Grid.

[BibT_eX]

[DOI]

Angeliki Lydia Antonia Syrri

IEEE Trans. Smart Grid, 2016

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Event-Driven User-Centric Middleware for Energy-Efficient Buildings and Public Spaces.

[BibT_eX]

[DOI]

IEEE Syst. J., 2016

Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.

[BibT_eX]

[DOI]

Massimo Alioto

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Frequency domain characterization of batteries for the design of energy storage subsystems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Distributed Software Infrastructure for Evaluating the Integration of Photovoltaic Systems in Urban Districts.

[BibT_eX]

[DOI]

Proceedings of the SMARTGREENS 2016, 2016

A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Unified Model of Power Sources for the Simulation of Electrical Energy Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Approximate Differential Encoding for Energy-Efficient Serial Communication.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Fast Thermal Simulation using SystemC-AMS.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Automated 3D immunofluorescence analysis of Dorsal Root Ganglia for the investigation of neural circuit alterations: a preliminary study.

[BibT_eX]

[DOI]

Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Low-overhead adaptive constrast enhancement and power reduction for OLEDs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Panel: Looking backwards and forwards.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals.

[BibT_eX]

[DOI]

Letícia Maria Bolzani Poehls

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Ultra-low power circuits using graphene p-n junctions and adiabatic computing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Addressing the Smart Systems design challenge: The SMAC platform.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

District Information Modeling and Energy Management.

[BibT_eX]

[DOI]

IT Prof., 2015

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs.

[BibT_eX]

[DOI]

Felipe Lavratti

Fabian Vargas

Proceedings of the 28th International Conference on VLSI Design, 2015

A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

An equation-based battery cycle life model for various battery chemistries.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

multiFLEX: Flexible Multi-utility, Multi-service Smart Metering Architecture for Energy Vectors with Active Prosumers.

[BibT_eX]

[DOI]

Enrico Pons

Dario Martellacci

Proceedings of the SMARTGREENS 2015, 2015

Top-Down Profiling of Application Specific Many-core Neuromorphic Platforms.

[BibT_eX]

[DOI]

Gianvito Urgese

Francesco Barchi

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

An automated design flow for approximate circuits based on reduced precision redundancy.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A tool-chain to foster a new business model for photovoltaic systems integration exploiting an Energy Community approach.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

Unsupervised HEp-2 mitosis recognition in indirect immunofluorescence imaging.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Enhancing Energy Awareness Through the Analysis of Thermal Energy Consumption.

[BibT_eX]

[DOI]

Proceedings of the Workshops of the EDBT/ICDT 2015 Joint Conference (EDBT/ICDT), 2015

A new distributed framework for integration of district energy data from heterogeneous devices.

[BibT_eX]

[DOI]

Francesco Gavino Brundu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

One-pass logic synthesis for graphene-based Pass-XNOR logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Energy Signature Analysis: Knowledge at Your Fingertips.

[BibT_eX]

[DOI]

Letícia Maria Bolzani Pöhls

Proceedings of the 2015 IEEE International Congress on Big Data, New York City, NY, USA, June 27, 2015

2014

Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Dynamic Indexing: Leakage-Aging Co-Optimization for Caches.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Row-based body-bias assignment for dynamic thermal clock-skew compensation.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Modeling of Physical Defects in PN Junction Based Graphene Devices.

[BibT_eX]

[DOI]

Sandeep Miryala

Matheus Oleiro

J. Electron. Test., 2014

Message from the program chairs.

[BibT_eX]

[DOI]

Giorgio C. Buttazzo

Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014

A framework for efficient evaluation and comparison of EES Models.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

miR-SEA: miRNA Seed Extension based Aligner Pipeline for NGS Expression Level Extraction.

[BibT_eX]

[DOI]

Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

An open-source framework for formal specification and simulation of electrical energy systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A compact macromodel for the charge phase of a battery with typical charging protocol.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

DIMCloud: A Distributed Framework for District Energy Simulation and Management.

[BibT_eX]

[DOI]

Francesco Gavino Brundu

Proceedings of the Internet of Things. User-Centric IoT, 2014

Automated generation of battery aging models from datasheets.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Modeling of the charging behavior of li-ion batteries based on manufacturer's data.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Design and implementation of a multi-standard event-driven energy management system for smart buildings.

[BibT_eX]

[DOI]

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Towards a Software Infrastructure for District Energy Management.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Pass-XNOR logic: A new logic style for P-N junction based graphene circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Thermal management of batteries using a hybrid supercapacitor architecture.

[BibT_eX]

[DOI]

Donghwa Shin

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Cache aging reduction with improved performance using dynamically re-sizable cache.

[BibT_eX]

[DOI]

Haroon Mahmood

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A cross-level verification methodology for digital IPs augmented with embedded timing monitors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Statistical Battery Models and Variation-Aware Battery Management.

[BibT_eX]

[DOI]

Donghwa Shin

Letícia Maria Veiras Bolzani Poehls

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Gelsius: A Literature-Based Workflow for Determining Quantitative Associations between Genes and Biological Processes.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2013

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Integration of Literature with Heterogeneous Information for Genes Correlation Scoring.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

Acceleration of coarse grain molecular dynamics on GPU architectures.

[BibT_eX]

[DOI]

J. Comput. Chem., 2013

A fully standard-cell delay measurement circuit for timing variability detection.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A framework with temperature-aware accuracy levels for battery modeling from datasheets.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Power modeling and characterization of Graphene-based logic gates.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices.

[BibT_eX]

[DOI]

Proceedings of the 14th Latin American Test Workshop, 2013

Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs.

[BibT_eX]

[DOI]

Felipe Lavratti

Fabian Vargas

Proceedings of the 14th Latin American Test Workshop, 2013

Enable sensor networks interoperability in smart public spaces through a service oriented approach.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

A statistical model of cell-to-cell variation in Li-ion batteries for system-level design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An automated framework for generating variable-accuracy battery models from datasheet information.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Exploration of different implementation styles for graphene-based reconfigurable gates.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

Delay model for reconfigurable logic gates based on graphene PN-junctions.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

SMAC: Smart Systems Co-design.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

HW-SW integration for energy-efficient/variability-aware computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A Novel Pipeline for V(D)J Junction Identification using RNA-Seq Paired-end Reads.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2013 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Barcelona, Spain, 11, 2013

A Preliminary Analysis on HEp-2 Pattern Classification: Evaluating Strategies Based on Support Vector Machines and Subclass Discriminant Analysis.

[BibT_eX]

[DOI]

Proceedings of the Biomedical Engineering Systems and Technologies, 2013

Classification of HEp-2 Staining Patterns in ImmunoFluorescence Images - Comparison of Support Vector Machines and Subclass Discriminant Analysis Strategies.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2013 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Barcelona, Spain, 11, 2013

2012

Design Techniques for NBTI-Tolerant Power-Gating Architectures.

[BibT_eX]

[DOI]

Hossein Karimiyan Alidash

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Design Techniques and Architectures for Low-Leakage SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

On-chip process variation-tracking through an all-digital monitoring architecture.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2012

Computer-aided techniques for chromogenic immunohistochemistry: Status and directions.

[BibT_eX]

[DOI]

Hossein Karimiyan Alidash

Comput. Biol. Medicine, 2012

Bellerophontes: an RNA-Seq data analysis framework for chimeric transcripts discovery based on accurate fusion model.

[BibT_eX]

[DOI]

Bioinform., 2012

Aging-aware caches with graceful degradation of performance.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Energy-optimal caches with guaranteed lifetime.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Applying textural features to the classification of HEp-2 cell patterns in IIF images.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Pattern Recognition, 2012

NBTI effects on tree-like clock distribution networks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Middleware services for network interoperability in smart energy efficient buildings.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

IR-drop analysis of graphene-based power distribution networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Application-specific memory partitioning for joint energy and lifetime optimization.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Characterization of Coarse Grain Molecular Dynamic Simulation Performance on Graphic Processing Unit Architectures.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2012 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Vilamoura, Algarve, Portugal, 1, 2012

A Novel Analysis Flow for Fused Transcripts Discovery from Paired-end RNA-Seq Data.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2012 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Vilamoura, Algarve, Portugal, 1, 2012

2011

Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating.

[BibT_eX]

[DOI]

Leandro Max de Lima Silva

IEEE Trans. Very Large Scale Integr. Syst., 2011

Automated Segmentation of Cells With IHC Membrane Staining.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Eng., 2011

A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

Power Efficient Variability Compensation Through Clustered Tunable Power-Gating.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue).

[BibT_eX]

[DOI]

Paula Helena Reyes-Herrera

Vijaykrishnan Narayanan

Kaushik Roy

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

miREE: miRNA Recognition Elements Ensemble.

[BibT_eX]

[DOI]

Karthikeyan Lingasubramanian

BMC Bioinform., 2011

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs.

[BibT_eX]

[DOI]

Felipe Lavratti

Fabian Vargas

Proceedings of the 12th Latin American Test Workshop, 2011

Buffering of frequent accesses for reduced cache aging.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Partitioned cache architectures for reduced NBTI-induced aging.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Binding Free Energy Calculation via Molecular Dynamics Simulations for a miRNA: mRNA Interaction.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2011, 2011

Improving Latent Semantic Analysis of Biomedical Literature Integrating UMLS Metathesaurus and Biomedical Pathways Databases.

[BibT_eX]

[DOI]

Proceedings of the Biomedical Engineering Systems and Technologies, 2011

A New Latent Semantic Analysis based Methodology for Knowledge Extraction from Biomedical Literature and Biological Pathways Databases.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2011, 2011

Motion Artifact Correction in ASL images: An Improved Automated Procedure.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2011

A novel framework for chimeric transcript detection based on accurate gene fusion model.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2011

2010

Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

NBTI-Aware Clustered Power Gating.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Dual-Vt assignment policies in ITD-aware synthesis.

[BibT_eX]

[DOI]

Microelectron. J., 2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Automated segmentation of tissue images for computerized IHC analysis.

[BibT_eX]

[DOI]

Comput. Methods Programs Biomed., 2010

Achieving the way for automated segmentation of nuclei in cancer tissue images through morphology-based approach: A quantitative evaluation.

[BibT_eX]

[DOI]

Comput. Medical Imaging Graph., 2010

Power-aware partitioning of data converters.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Generating power-hungry test programs for power-aware validation of pipelined processors.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Adaptive Task Migration Policies for Thermal Control in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Dynamic indexing: concurrent leakage and aging optimization for caches.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Analysis of NBTI-induced SNM degradation in power-gated SRAM cells.

[BibT_eX]

[DOI]

Paula Helena Reyes-Herrera

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Thermal-aware floorplanning exploration for 3D multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Aging effects of leakage optimizations for caches.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

An integrated thermal estimation framework for industrial embedded platforms.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Post-placement temperature reduction techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Panel: First commandment at least, do nothing well!

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

MicroRNA Target Prediction and Exploration through Candidate Binding Sites Generation.

[BibT_eX]

[DOI]

Proceedings of the CISIS 2010, 2010

An Automated Tool for Scoring Biomedical Terms Correlation Based on Semantic Analysis.

[BibT_eX]

[DOI]

Proceedings of the CISIS 2010, 2010

GPU acceleration of simulation tool for lipid-bilayers.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2010

2009

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.

[BibT_eX]

[DOI]

J. Embed. Comput., 2009

Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

On-chip Thermal Modeling Based on SPICE Simulation.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Data-Driven Clock Gating for Digital Filters.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

NBTI-aware power gating for concurrent leakage and aging optimization.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Placement-aware Clustering for Integrated Clock and Power Gating.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Using soft-edge flip-flops to compensate NBTI-induced delay degradation.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

NBTI-aware sleep transistor design for reliable power-gating.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Physically clustered forward body biasing for variability compensation in nanometer CMOS design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Enabling concurrent clock and power gating in an industrial design flow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Thermal-Aware Design Techniques for Nanometer CMOS Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.

[BibT_eX]

[DOI]

Integr., 2008

Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.

[BibT_eX]

[DOI]

Comput. Math. Appl., 2008

Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal sleep transistor synthesis under timing and area constraints.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Energy efficiency bounds of pulse-encoded buses.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Temperature-insensitive synthesis using multi-vt libraries.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

A Scalable Algorithmic Framework for Row-Based Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Automated Discrimination of Pathological Regions in Tissue Images: Unsupervised Clustering vs. Supervised SVM Classification.

[BibT_eX]

[DOI]

Proceedings of the Biomedical Engineering Systems and Technologies, 2008

Fully-Automated Segmentation of Tumor Areas in Tissue Confocal Images - Comparison between a Custom Unsupervised and a Supervised SVM Approach.

[BibT_eX]

Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

Segmentation of nuclei in cancer tissue images: Contrasting active contours with morphology-based approach.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008

2007

In Memoriam: Margarida F. Jacome.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Control and datapath decoupling in the design of a NoC switch: area, power and performance implications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2007

Timing-driven row-based power gating.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.

[BibT_eX]

[DOI]

Simone Medardoni

Davide Bertozzi

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Locality-driven architectural cache sub-banking for leakage energy reduction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.

[BibT_eX]

[DOI]

Antonio Pullini

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Architectural leakage-aware management of partitioned scratchpad memories.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Early Power-Aware Design & Validation: Myth or Reality?

[BibT_eX]

Gila Kamhi

Sarah Miller

Stephen Bailey Mentor

Proceedings of the 44th Design Automation Conference, 2007

Selection of Tumor Areas and Segmentation of Nuclear Membranes in Tissue Confocal Images: A Fully Automated Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2007

Gene-Markers Representation for Microarray Data Integration.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, 2007

2006

Low-energy RGB color approximation for digital LCD interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2006

Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

TOM: a web-based integrated approach for identification of candidate disease genes.

[BibT_eX]

[DOI]

Nucleic Acids Res., 2006

Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

Optimized Technique for Dna Structural Properties Discovering.

[BibT_eX]

[DOI]

Int. J. Artif. Intell. Tools, 2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Mining Gene Sets for Measuring Similarities.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Low-energy pixel approximation for DVI-based LCD interfaces.

[BibT_eX]

[DOI]

A. Nurrachmat

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

STV-Cache: a leakage energy-efficient architecture for data caches.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Low-power design tools: are EDA vendors taking this matter seriously?

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Thermal resilient bounded-skew clock tree optimization methodology.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Enabling fine-grain leakage management by voltage anchor insertion.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Computer-Based Medical Systems (CBMS 2006), 2006

2005

Automated DNA fragments recognition and sizing through AFM image processing.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Technol. Biomed., 2005

Energy-efficient bus encoding for LCD digital display interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2005

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation.

[BibT_eX]

[DOI]

Pietro Babighian

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Automatic intrinsic DNA curvature computation from AFM images.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Eng., 2005

Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Energy-Aware System-on-Chip for 5 GHz Wireless LANs.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Frame Buffer Energy Optimization by Pixel Prediction.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Energy-Efficient Color Approximation for Digital LCD Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Zero clustering: an approach to extend zero compression to instruction caches.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Low-overhead state-retaining elements for low-leakage MTCMOS design.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Memory energy minimization by data compression: algorithms, architectures and implementation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Leakage power optimization in standard-cell designs.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

RTL power estimation and optimization.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

A Low-Power Encoding Scheme for GigaByte Video Interfaces.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Power-aware clock tree planning.

[BibT_eX]

[DOI]

Monica Donno

Luca Mazzoni

Proceedings of the 2004 International Symposium on Physical Design, 2004

Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Post-layout leakage power minimization based on distributed sleep transistor insertion.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Crosstalk energy reduction by temporal shielding.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Reducing cache misses by application-specific re-configurable indexing.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Energy-efficient bus encoding for LCD displays.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating.

[BibT_eX]

[DOI]

Pietro Babighian

Proceedings of the 2004 Design, 2004

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks.

[BibT_eX]

[DOI]

Pietro Babighian

Proceedings of the 2004 Design, 2004

Techniques for Enhancing Computation of DNA Curvature Molecules.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004

2003

Scheduling battery usage in mobile systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Discharge Current Steering for Battery Lifetime Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Statistical Power Estimation of Behavioral Descriptions.

[BibT_eX]

[DOI]

B. Arts

N. van der Eng

Marc J. M. Heijligers

Proceedings of the Integrated Circuit and System Design, 2003

Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Energy-efficient data scrambling on memory-processor interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Increasing the locality of memory access patterns by low-overhead hardware address relocation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining wire swapping and spacing for low-power deep-submicron buses.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A novel architecture for power maskable arithmetic units.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Improving the Efficiency of Memory Partitioning by Address Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Clock-tree power optimization based on RTL clock-gating.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Energy-aware design techniques for differential power analysis protection.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Guest editorial: low-power electronics and design.

[BibT_eX]

[DOI]

Ingrid Verbauwhede

IEEE Trans. Very Large Scale Integr. Syst., 2002

Minimizing memory access energy in embedded systems by selective instruction compression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Discharge current steering for battery lifetime optimization.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

An adaptive data compression scheme for memory traffic minimization in processor-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Enhanced clustered voltage scaling for low power.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Wire Placement for Crosstalk Energy Minimization in Address Buses.

[BibT_eX]

[DOI]

Luca Macchiarulo

Proceedings of the 2002 Design, 2002

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Stream synthesis for efficient power simulation based on spectral transforms.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Parameterized RTL power models for soft macros.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Discrete-time battery models for system-level low-power design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Synthesis of power-managed sequential components based oncomputational kernel extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Guest Editor's Introduction: Dynamic Power Management of Electronic Systems.

[BibT_eX]

IEEE Des. Test Comput., 2001

Low-energy for deep-submicron address buses.

[BibT_eX]

[DOI]

Luca Macchiarulo

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Current-controlled policies for battery-driven dynamic power management.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Fast characterization of RTL power macromodels.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

On-the-fly layout generation for PTL macrocells.

[BibT_eX]

[DOI]

Luca Macchiarulo

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Extending lifetime of portable systems by battery scheduling.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Glitch power minimization by selective gate freezing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Power optimization of technology-dependent circuits based on symbolic computation of logic implications.

[BibT_eX]

[DOI]

R. Iris Bahar

Ernest T. Lampe

ACM Trans. Design Autom. Electr. Syst., 2000

Symbolic optimization of interacting controllers based onredundancy identification and removal.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A multilevel engine for fast power simulation of realistic inputstreams.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Power Models for Semi-autonomous RTL Macros.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

RTL Estimation of Steering Logic Power.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

Battery-Driven Dynamic Power Management of Portable Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

Power Macromodeling for a High Quality RT-Level Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Supporting system-level power exploration for DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Regression-based RTL power models for controllers.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A Discrete-Time Battery Model for High-Level Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Synthesis of application-specific memories for power optimization in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1999

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Selective instruction compression for memory energy reduction in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Analysis of memory accesses in embedded systems.

[BibT_eX]

[DOI]

Luca Nosetti

Charlie Solomon

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Peak power constrained test sets: generation heuristics and experiments.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Low-power implementation of a residue-to-weighted conversion unit for a 5-moduli RNS.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Parameterized RTL power models for combinational soft macros.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Regression-Based Macromodeling for Delay Estimation of Behavioral Components.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Clustered Table-Based Macromodels for RTL Power Estimation.

[BibT_eX]

[DOI]

Roberto Corgnati

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Glitch Power Minimization by Gate Freezing.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Power optimization of core-based systems by address bus encoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

High-level power modeling, estimation, and optimization.

[BibT_eX]

[DOI]

Massoud Pedram

Fabio Somenzi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Telescopic units: a new paradigm for performance optimization of VLSI designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Timed Supersetting and the Synthesis of Telescopic Units.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Power Estimation of Behavioral Descriptions.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Address Bus Encoding Techniques for System-Level Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

In-Place Power Optimization for LUT-Based FPGAs.

[BibT_eX]

[DOI]

Balakrishna Kumthekar

Fabio Somenzi

Proceedings of the 35th Conference on Design Automation, 1998

Computational Kernels and their Application to Sequential Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Formal verification of digital systems by automatic reduction of data paths.

[BibT_eX]

[DOI]

Bernard Plessier

Fabio Somenzi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Algebraic Decision Diagrams and Their Applications.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1997

Testing Core-Based Systems: A Symbolic Methodology.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1997

System-level power optimization of special purpose applications: the beach solution.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Fast power estimation for deterministic input streams.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Markovian analysis of large finite state machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Algorithms for approximate FSM traversal based on state space decomposition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Automatic state space decomposition for approximate FSM traversal based on circuit analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Symbolic computation of logic implications for technology-dependent low-power synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Enhancing FSM Traversal by Temporary Re-Encoding.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Exact Computation of the Entropy of a Logic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

BDD-based testability estimation of VHDL designs.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Using connectivity and spectral methods to characterize the structure of sequential logic circuits.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1995

Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

Computing the Maximum Power Cycles of a Sequential Circuit.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

A test generation program for sequential circuits.

[BibT_eX]

[DOI]