Enrico Costenaro
According to our database1,
Enrico Costenaro
authored at least 17 papers
between 2011 and 2015.
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Bibliography
2015
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF).
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
J. Electron. Test., 2013
Pulse-length determination techniques in the rectangular single event transient fault model.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011