Enric Morancho

Orcid: 0000-0003-2403-8145

According to our database1, Enric Morancho authored at least 31 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
Security and RAS in the Computing Continuum.
CoRR, 2024

Hypervisor Extension for a RISC-V Processor.
CoRR, 2024

Compute units in OpenMP: Extensions for heterogeneous parallel programming.
Concurr. Comput. Pract. Exp., 2024

Malware Detection on Linux Using Runtime Opcode Tracing.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

Special Session: Security and RAS in the Computing Continuum.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023
Heterogeneous programming using OpenMP and CUDA/HIP for hybrid CPU-GPU scientific applications.
Int. J. High Perform. Comput. Appl., September, 2023

An automotive case study on the limits of approximation for object detection.
J. Syst. Archit., 2023

2022
Two examples of approximate arithmetic to reduce hardware complexity and power consumption.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021
Multi-GPU Parallelization of the NAS Multi-Zone Parallel Benchmarks.
IEEE Trans. Parallel Distributed Syst., 2021

Multi-GPU systems and Unified Virtual Memory for scientific applications: The case of the NAS multi-zone parallel benchmarks.
J. Parallel Distributed Comput., 2021

2016
Unum: Adaptive Floating-Point Arithmetic.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
A Vector Implementation of Gaussian Elimination over GF(2): Exploring the Design-Space of Strassen's Algorithm as a Case Study.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

2014
A Hybrid Implementation of Hamming Weight.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

2013
A Square Block Format for Symmetric Band Matrices.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

2011
Assessing Accelerator-Based HPC Reverse Time Migration.
IEEE Trans. Parallel Distributed Syst., 2011

2009
Linux Kernel Compaction through Cold Code Swapping.
Trans. High Perform. Embed. Archit. Compil., 2009

High-Performance Reverse Time Migration on GPU.
Proceedings of the 2009 International Conference of the Chilean Computer Science Society, 2009

On reducing misspeculations in a pipelined scheduler.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2007
A comparison of two policies for issuing instructions speculatively.
J. Syst. Archit., 2007

On reducing energy-consumption by late-inserting instructions into the issue queue.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
An Enhancement for a Scheduling Logic Pipelined over two Cycles .
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
On the Practical use of Variable Elimination in Constraint Optimization Problems: 'Still-life' as a Case Study.
J. Artif. Intell. Res., 2005

2004
A Mechanism for Verifying Data Speculation.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Solving 'Still Life' with Soft Constraints and Bucket Elimination.
Proceedings of the Principles and Practice of Constraint Programming, 2003

2002
Address Prediction and Recovery Mechanisms.
PhD thesis, 2002

2001
Recovery Mechanism for Latency Misprediction.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000
Two-Level Address Storage and Address Prediction (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Looking at History to Filter Allocations in Prediction Tables.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
A General Algorithm for Tiling the Register Level.
Proceedings of the 12th international conference on Supercomputing, 1998

Split Last-Address Predictor.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1996
A Unified Transformation Technique for Multilevel Blocking.
Proceedings of the Euro-Par '96 Parallel Processing, 1996


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