Enric Herrero

According to our database, Enric Herrero authored at least 5 papers between 2008 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Capturing vulnerability variations for register files.

Javier Carretero, Enric Herrero, Matteo Monchiero, Tanausú Ramírez, Xavier Vera

Proceedings of the Design, Automation and Test in Europe, 2013

2011

New reliability mechanisms in memory design for sub-22nm technologies.

Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010

Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.

Enric Herrero, José González, Ramon Canal

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Power-Efficient Spilling Techniques for Chip Multiprocessors.

Enric Herrero, José González, Ramon Canal

Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2008

Distributed cooperative caching.

Enric Herrero, José González, Ramon Canal

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008